Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals
Takuji Ogihara,Shinichi Murai,Yuzo Takamatsu,Kozo Kinoshita,Hideo Fujiwara +4 more
- pp 71-78
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TLDR
A program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals by using shift-in function of SRLs by using path sensitization technique with 14 signal values.Abstract:
This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of this program are test generation with automatic decision of I/O mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches (SRLs) by using shift-in function of SRLs.read more
Citations
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Proceedings ArticleDOI
Evaluation and improvement of Boolean comparison method based on binary decision diagrams
TL;DR: The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times faster than times reported in the literature.
Journal ArticleDOI
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
TL;DR: New concepts and algorithms used to generate tests for VLSI scan-design circuits are described, including a low-cost fault-independent algorithm, a fault-oriented algorithm, and an algorithm for dynamic test set compaction.
Journal ArticleDOI
Gate-level test generation for sequential circuits
TL;DR: The basic concepts, examples, advantages, and limitations of representative methods are reviewed in detail and the relationship between gate-level sequential circuit ATPG and the partial scan design is discussed.
Proceedings ArticleDOI
Test generation for ultra-large circuits using ATPG constraints and test-pattern templates
P. Wohl,J. Waicukauski +1 more
TL;DR: A method is described that supports defining general pattern restrictions that are partitioned to allow efficient test generation.
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TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
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ON THE ACCELERATION OF TEST GENERATION ALGORlTHMS
H. Fujiwara,T. Shimono +1 more
TL;DR: In this paper, a test generation algorithm called FAN (FANout-oriented test generation) is presented, which is faster and more efficient than the PODEM algorithm reported by Goel.