Learning and evolution are two fundamental forms of adaptation. There has been a great interest in combining learning and evolution with artificial neural networks (ANNs) in recent years. This paper: 1) reviews different combinations between ANNs and evolutionary algorithms (EAs), including using EAs to evolve ANN connection weights, architectures, learning rules, and input features; 2) discusses different search operators which have been used in various EAs; and 3) points out possible future research directions. It is shown, through a considerably large literature review, that combinations between ANNs and EAs can lead to significantly better intelligent systems than relying on ANNs or EAs alone.

/pdf/evolving-artificial-neural-networks-4kzrbu7pkn.pdf

Evolving artificial neural networks

This paper surveys locally weighted learning, a form of lazy learning and memory-based learning, and focuses on locally weighted linear regression. The survey discusses distance functions, smoothing parameters, weighting functions, local model structures, regularization of the estimates and bias, assessing predictions, handling noisy data and outliers, improving the quality of predictions by tuning fit parameters, interference between old and new data, implementing locally weighted learning efficiently, and applications of locally weighted learning. A companion paper surveys how locally weighted learning can be used in robot learning and control.

/pdf/locally-weighted-learning-4parann0z5.pdf

Locally Weighted Learning

Metaheuristics are the most exciting development in approximate optimization techniques of the last two decades. They have had widespread successes in attacking a variety of difficult combinatorial optimization problems that arise in many practical areas. This bibliography provides a classification of a comprehensive list of 1380 references on the theory and application of metaheuristics. Metaheuristics include but are not limited to constraint logic programming; greedy random adaptive search procedures; natural evolutionary computation; neural networks; non-monotonic search strategies; space-search methods; simulated annealing; tabu search; threshold algorithms and their hybrids. References are presented in alphabetical order under a number of subheadings.

Metaheuristics: A bibliography

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

In a previous work it was argued that by studying evolved designs of gradually increasing scale, one might be able to discern new, efficient, and generalisable principles of design. These ideas are tested in the context of designing digital circuits, particularly arithmetic circuits. This process of discovery is seen as a principle extraction loop in which the evolved data is analysed both phenotypically and genotypically by processes of data mining and landscape analysis. The information extracted is then fed back into the evolutionary algorithm to enhance its search capabilities and hence increase the likelihood of identifying new principles which explain how to build systems which are too large to evolve.

Principles in the Evolutionary Design of Digital Circuits—Part II

Evolving hardware with genetic learning: a first step towards building a Darwin machine

This paper describes a function-level Evolvable Hardware (EHW). EHW is hardware which is built on programmable logic devices (e.g. PLD and FPGA) and whose architecture can be reconfigured by using a genetic learning to adapt to new unknown environments in real time. It is demonstrated that the function-level hardware evolution can attain much higher performances than the gate-level evolution, in neural network applications (e.g. two-spiral). VLSI architecture of the functionbased FPGA dedicated to function level evolution is also described.

Hardware Evolution at Function Level

This paper describes Evolvable Hardware (EHW) with genetic learning. EHW is hardware which is built on programmable logic devices (e.g. PLD and FPGA) and whose architecture can be reconfigured by using genetic learning to adapt to the new environment. There are two types of hardware evolutions; gate-level and function-level. As examples of gate-level evolution, a pattern recognition system and a welding robot controller are described. Then, function-level EHW is introduced. It is demonstrated that function-level hardware evolutions can attain high performances as in neural network applications (e.g. two spirals). New FPGA architecture for function-level evolution is also described.

Evolvable hardware with genetic learning

This paper describes Evolvable Hardware (EHW) and its applications to pattern recognition and fault-torelant systems. EHW can change its own hardware structure to adapt to the environment whenever environmental changes (including hardware malfunction) occur. EHW is implemented on a PLD(Programmable Logic Device)-like device whose architecture can be altered by re-programming the architecture bits. Through genetic algorithms, EHW finds the architecture bits which adapt best to the environment, and changes its hardware structure accordingly.

Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems

This paper describes a parallel associative processor, lXM2, developed mainly for semantic network processing. IXM2 consists of 64 associative processors and 9 network processors, having a total of 256K words of associative memory. The large associative memory enables 65,536 semantic network nodes to be processed in parallel and reduces the order of algorithmic complexity to O( 1) in,basic semantic net operations. It is shown that IXM2 has computing power comparable to that of a Connection Machine. Programming for lXM2 is performed with the knowledge representation language IXL, a superset of Prolog, so that IXM2 can be utilized as a back-end to AI workstations.

Tatsumi Furuya

Papers

Evolving hardware with genetic learning: a first step towards building a Darwin machine

Hardware Evolution at Function Level

Evolvable hardware with genetic learning

Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems

IXM2: a parallel associative processor