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Design Of Analog Cmos Integrated Circuits

This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

In the fifth-generation (5G) mobile communication system, various service requirements of different communication environments are expected to be satisfied. As a new evolution network structure, heterogeneous network (HetNet) has been studied in recent years. Compared with homogeneous networks, HetNets can increase the opportunity in the spatial resource reuse and improve users’ quality of service by developing small cells into the coverage of macrocells. Since there is mutual interference among different users and the limited spectrum resource in HetNets, however, efficient resource allocation (RA) algorithms are vitally important to reduce the mutual interference and achieve spectrum sharing. In this article, we provide a comprehensive survey on RA in HetNets for 5G communications. Specifically, we first introduce the definition and different network scenarios of HetNets. Second, RA models are discussed. Then, we present a classification to analyze current RA algorithms for the existing works. Finally, some challenging issues and future research trends are discussed. Accordingly, we provide two potential structures for 6G communications to solve the RA problems of the next-generation HetNets, such as a learning-based RA structure and a control-based RA structure. The goal of this article is to provide important information on HetNets, which could be used to guide the development of more efficient techniques in this research area.

/pdf/a-survey-on-resource-allocation-for-5g-heterogeneous-4gmdtz8zbn.pdf

A Survey on Resource Allocation for 5G Heterogeneous Networks: Current Research, Future Trends, and Challenges

https://hal.archives-ouvertes.fr/hal-02395411/document

Agri-food 4.0: A survey of the supply chains and technologies for the future agriculture

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Design Of Integrated Circuits For Optical Communications

Clock and data recovery CDR is an essential part in high-speed telecommunication systems. The CDR is used to extract the clock and re-time the received data, which allows a synchronous operation to recover the transmitted signal. In optical access networks, electrical CDR or optical CDR implementations can be used. However, there are no clear guidelines or recommendations on which CDR implementation should be adopted for better performance. These missing clear recommendations are because the electrical CDR requires electronics design expertise whereas the optical CDR requires optical design expertise. Consequently, in this paper, an all-digital CDR, designed and implemented on the field-programmable gate array platform, and an optical CDR, developed by using fiber Bragg grating technology on the OptiSystem platform, are presented. Furthermore, the integration of these 2 CDR implementations with the optical access network is implemented, and their performance is evaluated for various transmission rates and communication distances. Finally, a comparative study in terms of the bit error rate between the all-digital CDR and the optical CDR is presented.

Electrical and optical clock and data recovery in optical access networks: a comparative study

The detection processor is a part of an implantable integrated device used for detection of an electrographic seizure onset. The system is supposed to acquire the neural signals from 1024 electrodes implanted in the brain tissues, amplify the acquired signals, and then process them using the seizure detection processor to detect the occurrence of a seizure. Based on the decision of the processor, a stimulation signal can be applied to a number of the implanted electrodes to block the seizure progression.

Low-power implantable seizure detection processor

Integrated Fiber (IF) approach for optical signal processing offers significant advantages in both performance and cost when compared to conventional electrical processing. The main problem in optical single processing is to maintain the data in the optical domain without converting it to the electrical domain. Currently, many devices have been proposed for processing the data in the optical domain. The Wavelength Optical Crossbar (WOC), one of the important devices in optical networks, has been developed based on the phenomenon of wavelength exchanging. High-NonLinear Dispersion Shifted Fiber (HNL-DSF) provides a good performance due to the high mixing efficiency. In this paper, we will study the impacts of changing the HNL-DSF parameter on the wavelength exchanging.

http://ieeexplore.ieee.org/iel7/6747513/6766373/06766402.pdf

The impact of changing HNL-DSF parameters on wavelength exchanging

The recorded Electroencephalography (EEG) data comes with a large size due to the high sampling rate. Therefore, large space and more bandwidth are required for storing and transmitting the EEG data. Thus, preprocessing and compressing the EEG data is a very important part in order to transmit and store it efficiently with less bandwidth and less space. The objective of this paper is to develop an efficient system for EEG data compression. In this system, the recorded EEG data are firstly preprocessed in the preprocessing unit. Standardization and segmentation of EEG data are done in this unit. Then, the resulting EEG data are passed to the compression unite. The compression unit composes of a lossy compression algorithm followed by a lossless compression algorithm. The lossy compression algorithm transforms the randomness EEG data into data with high redundancy. Subsequently, A lossless compression algorithm is added to investigate the high redundancy of the resulting data to get high Compression Ratio (CR) without any additional loss. In this paper, the Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) are proposed as a lossy compression algorithm. Furthermore, Arithmetic Encoding and Run Length Encoding (RLE) are proposed as a lossless compression algorithm. We calculate the total compression and reconstruction time (T), Root Mean Square Error (RMSE), and CR in order to evaluate the proposed system. Simulation results show that adding RLE after the DCT algorithm gives the best performance in terms of compression ratio and complexity. Using the DCT as a lossy compression algorithm followed by the RLE as a lossless compression algorithm gives CR=90% at RMSE=0.14 and more than 95% of CR at RMSE=0.2.

Hybrid Compression Techniques for EEG Data Based on Lossy/Lossless Compression Algorithms

Optical Packet Switching (OPS) is a promising technology to enable next-generation high-speed IP networks. One of the main components in an OPS network is the optical switch architecture that provides the basic functionality of switching packets from input ports to the desired output ports while maintaining data in the optical domain. In asynchronous OPS networks, contention may arise when two or more packets need to be directed to the same output source leading to packet loss and thus lower switching performance. Optical buffering, which is implemented by fiber delay lines (FDLs), is one of the approaches used for resolving contention. In this paper, we focus on the design a new FDL-based switch architecture that resolves packet contention in asynchronous OPS networks and achieves the same performance as that of best known architectures but with a reduced hardware complexity. Our analysis shows that, the proposed architectures possess some interesting properties as compared to existing designs. For example, for the same packet loss level, the proposed architecture requires a number of switch ports less than that used in generic architecture.

Tawfik Ismail

Papers

Electrical and optical clock and data recovery in optical access networks: a comparative study

Low-power implantable seizure detection processor

The impact of changing HNL-DSF parameters on wavelength exchanging

Hybrid Compression Techniques for EEG Data Based on Lossy/Lossless Compression Algorithms

An enhanced OPS architecture with optical buffers