T
Te-Yu Liu
Researcher at TSMC
Publications - 3
Citations - 10
Te-Yu Liu is an academic researcher from TSMC. The author has contributed to research in topics: Parasitic capacitance & Design layout record. The author has an hindex of 1, co-authored 3 publications receiving 9 citations.
Papers
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Patent
Method for analyzing interconnect process variation
TL;DR: In this paper, a method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided.
Proceedings ArticleDOI
A comprehensive solution for BEOL variation characterization and modeling
Katherine Chiang,Jun-Fu Huang,Cheng Tai-Yu,Cheng Hsiao,Joshua Sun,Chun Cheng,Kuo-Pei Lu,Ke-Wei Su,Chung-Kai Lin,Kevin Chen,King-Ho Tam,Te-Yu Liu,Ke-Ying Su,Min-Chie Jeng +13 more
TL;DR: In this paper, a more comprehensive solution for BEOL variations characterization and modeling associated with statistical Monte Carlo simulation is proposed, where the BEOL contribution is becoming more important with device scaling and simulation results with conventional corner model may not always produce optimal design margin.
Patent
Method of designing circuit layout and system for implementing the same
TL;DR: In this article, a method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file and an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector.