An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length λ.

Nano-wire resistance model

A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.

Computer-implemented method and computing system for designing integrated circuit by considering process variations of wire

A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.

Determining eco aggressor nets during incremental extraction

A method for simulating an integrated circuit (IC) is provided. The method includes parsing an IC and loading the IC into memory and forming a table model including parameter values for at least one circuit component in the IC, the parameter values selected from a portion of a parameter space, storing a data value associated with the parsing of the IC and the table model in a database accessible through a cloud computing environment, the data value comprising a metadata associated with the data value, loading, to a processor, at least one of the data value or the metadata from the database, modifying the data value or the metadata that is loaded in the processor, according to the portion of the parameter space, and performing an analysis on at least one block of the IC according to the data value or the metadata that is loaded in the processor.

Integrated circuit simulation with data persistency for efficient memory usage

Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wn and a height Hn are estimated for each volume element n in the conducting structure. Furthermore, the local resistivity ρn for each volume element n is estimated based on a function that is dependent upon the length L of the conducting structure and the width Wn and height Hn of the volume element n. The resistance of a conducting structure is estimated in dependence upon the resistivity ρn for each of the volume elements n in the plurality of volume elements in the conducting structure.

Computationally efficient nano-scale conductor resistance model

A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Wen-Cheng Huang

Papers

Method for analyzing interconnect process variation