There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Data Mining Practical Machine Learning Tools and Techniques

This paper reviews the state of the art of field- programmable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic.

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FPGA Design Methodology for Industrial Control Systems—A Review

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

Design and Analysis ofFault-Tolerant Digital Systems: B. W. JOHNSON (Addison Wesley, 1989,577 pp., £41.35) The book provides an introduction to the important aspects of designing fault-tolerant systems, and an evaluation of how well the reliability goals have been achieved. The book is mainly oriented towards a final year undergraduate course on fault-tolerant computing, primarily with an implementation bias. In chapters 1 and 2, definitions and basic terminology are covered, which sets the stage for the remaining chapters, and provides the background and motivation for the remainder of the book. Chapter 3 provides a thorough analysis of fault-tolerance techniques and concepts. This chapter in particular is remarkably well written, covering the issues of hardware and information redundancy, which form the mainstay offault-tolerant computing. Subsequent chapters on the use and evaluation of the various approaches illustrate the principles as they have been put into practice. At the end of chapter 5, small projects that allow the reader to apply the material presented in the preceding chapters are included. The resurgence of interest in fault-tolerance with the emergence of VLSI is the theme of chapter 6, focussing on designing fault-tolerant systems in a VLSI environment. The problems and opportunities presented by VLSI are discussed and the use of redundancy techniques in order to enhance manufacturing yield and to provide in-service reliability are reviewed. The final chapter covers testing, design for testability and testability analysis, which must be considered during each phase of the design process to guarantee that resulting designs can be thoroughly tested. Each chapter is followed by a summary of the key issues and concepts presented therein, and a separate list of references, which makes it easily readable. In addition, there is a reading list with more comprehensive and specialised references devoted to each chapter. Overall, the book is well written, and contains a great deal of information in 577 pages. The book has a definite implementation bias, and draws considerably on the author's experience in industry, particularly reflected in the projects accompanying chapter 5. The book should be a useful addition to a library, and a suitable text to accompany a lecture course on fault-tolerant computing. R. RAMASWAMI, Department ofComputation, UMIST

Book Review: Design and Analysis of Fault-Tolerant Digital SystemsDesign and Analysis of Fault-Tolerant Digital Systems: JohnsonB. W. (Addison Wesley, 1989, 577 pp., £41.35)

Purpose – Low-power consumption has become an important issue that cannot be ignored in system-on-chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. The purpose of this paper is to demonstrate an accurate and fast power estimation technique. Design/methodology/approach – The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings – The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of...

Power analysis approach and its application to IP-based SoC design

Low power is becoming a more crucial performance metrics in system-on-chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation.

This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm is implemented for the generation of sequences of input signals during the power estimation procedure. The genetic algorithm concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte Carlo zero-delay simulation is performed for individual IP core and bus at a high level. By the simple addition of these cores/buses, power is predicted by a novel macromodel function. The metamodeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In the experiments with the IP-based SoC system, the average error is estimated at 11.42%.

Power macromodeling technique and its application to SoC-based design

As Wireless Sensor Network-based solutions are proliferating they are facing new challenges: they must be capable of adapting to rapidly changing environments and requirements while their nodes should have low power consumption as they usually run on batteries. Moreover, the security aspect is crucial since they frequently transmit and process very sensitive data, while it is important to be able to support real-time video or processed images over their limited bandwidth links. SMART targets to design and implement a highly reconfigurable Wireless Visual Sensor Node (WVSN) defined as a miniaturized, light-weight, secure, low-cost, battery powered sensing device, enriched with video and data compression capabilities.

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Secure, Mobile Visual Sensor Networks Architecture

Remote reprogramming capabilities are one of the major concerns in WSN platforms due to the limitations and constraints that low power wireless nodes poses, especially when energy efficiency during the reprogramming process is a critical factor for extending the battery life of the devices. Moreover, WSNs are based on low-rate protocols in which as greater the amount of data is sent, the more the possibility to lose packets during the transmitting process is. In order to overcome these limitations, in this work a novel on-the-fly reprogramming technique for modifying and updating the application running on the wireless sensor nodes is designed and implemented, based on a partial reprogramming mechanism that significantly reduces the size of the files to be downloaded to the nodes, therefore diminishing their power/time consumption. This powerful mechanism also addresses multi-experimental capabilities because it provides the possibility to download, manage, test and debug multiple applications into the wireless nodes, based on a memory map segmentation of the core. Being an on-the-fly reprogramming process, no additional resources to store and download the configuration file are needed.

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On-the-fly dynamic reprogramming mechanism for increasing the energy efficiency and supporting multi-experimental capabilities in WSNs

This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL) Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis Nevertheless, partition methods imply approximations that produce inaccurate results We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size

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Teresa Riesgo

Papers

Power analysis approach and its application to IP-based SoC design

Power macromodeling technique and its application to SoC-based design

Secure, Mobile Visual Sensor Networks Architecture

On-the-fly dynamic reprogramming mechanism for increasing the energy efficiency and supporting multi-experimental capabilities in WSNs

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level