T
Tetsuya Hirose
Researcher at Osaka University
Publications - 194
Citations - 2164
Tetsuya Hirose is an academic researcher from Osaka University. The author has contributed to research in topics: CMOS & Subthreshold conduction. The author has an hindex of 18, co-authored 188 publications receiving 1884 citations. Previous affiliations of Tetsuya Hirose include Kobe University & Hokkaido University.
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Journal ArticleDOI
A Highly Sensitive Thermosensing CMOS Circuit Based on Self-Biasing Circuit Technique
TL;DR: In this article, a self-biasing circuit based on a thermosensing CMOS circuit that changes its internal voltage steeply at a critical temperature was developed, which can be used as over-temperature and over-current protectors for LSI circuits.
Journal ArticleDOI
Characterization of deep interface states in SiO2/B-doped diamond using the transient photocapacitance method
TL;DR: In this article, a diamond metal oxide semiconductor structure with a silicon dioxide (SiO2) film as the gate dielectric on B-doped diamond grown by a high-power-density microwave-plasma chemical vapor deposition method was fabricated.
Neuromorphic MOS Circuits Exhibiting Precisely Timed Synchronization with Silicon Spiking Neurons and Depressing Synapses (Special Issue on Nonlinear Circuits and Signal Processing)
TL;DR: A novel analog circuit mimicking characteristics of spike-timing dependent plasticity (STDP) was proposed to construct a neural network that exhibits robust synchronization in a noisy environment and timing jitter among the neurons was significantly reduced with depressing synapses.
Proceedings ArticleDOI
Temperature Compensated Nano-Ampere CMOS Current Reference Circuit Using Small Offset Voltage
Noise-Induced Phase Synchronization among Nonidentical Analog CMOS Oscillators
TL;DR: This paper demonstrates that identical oscillators can be synchronized by artificial noises, and explores the effect of mismatches among oscillator circuits, and demonstrates that phase differences among nonidentical oscillators are suppressed by noises if the threshold voltage difference of a dominant MOSFET in the circuits is smaller than 12 mV.