There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

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Differential Power Analysis

N G van Kampen 1981 Amsterdam: North-Holland xiv + 419 pp price Dfl 180 This is a book which, at a lower price, could be expected to become an essential part of the library of every physical scientist concerned with problems involving fluctuations and stochastic processes, as well as those who just enjoy a beautifully written book. It provides an extensive graduate-level introduction which is clear, cautious, interesting and readable.

https://iopscience.iop.org/article/10.1088/0031-9112/34/4/040/pdf

Stochastic Processes in Physics and Chemistry

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

The fundamental question of how much we can ultimately reduce the phase noise of a lumped, inductorless oscillator through careful design is addressed and it is shown that the fluctuation dissipation theorem of thermodynamics imposes a 1,ower limit on the phase noise. An analytical formulation of this limit is presented and it is shown that the phase noise of ring oscillators with long-channel MOS devices is closer to this limit compared to that of the relaxation oscillators or ring oscillators with short channel MOS devices.

/pdf/lumped-inductorless-oscillators-how-far-can-they-go-30upkil3gq.pdf

Lumped, inductorless oscillators: how far can they go?

Generating quadrature phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common For example, [1] uses LC-VCOs followed by 2:1 dividers to generate the half-rate clocks for both TX and RX in a 28Gb/s transceiver However, such an approach tends to be power- and area-inefficient for multi-lane implementations at data rates of 25Gb/s and beyond

A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS

This work presents a stochastic model for the observed signal of biosensors, a model that predicts the signal fluctuation of the system and the SNR associated with it using a Markov chain process. In the process, transition probabilities are derived from the target and probe binding kinetics in view of statistical motion and random walk events. Based on this model, we are able to estimate the settling time, power-spectral density (PSD), and signal to noise ratio (SNR) of general affinity-based biosensors. The effects of scaling from macroscopic to microscopic regimes are also studied, which indicate a fundamental tradeoff between settling time (speed) and signal fluctuation (noise). The model is also applied to analyze the behavior of a DNA hybridization electronic detector.

/pdf/effects-of-scaling-on-the-snr-and-speed-of-biosensors-1rqcqy7vo7.pdf

Effects of scaling on the SNR and speed of biosensors

General conditions for minimizing the noise figure of any linear two-port are reviewed before considering the specific case of a MOSFET low-noise amplifier (LNA). It is shown that the minimum noise figure cannot be obtained over an arbitrarily large bandwidth with networks of low order. For narrowband operation, however, one may construct simple amplifiers whose noise figure and power gain are close to the theoretical optima allowed within an explicit power constraint, and which simultaneously present a specified impedance to the driving source. The effects of overlap (drain-gate) capacitance, short-channel carrier heating, substrate resistance (“epi noise”), and gate interconnect resistance are also considered. Amplifier noise figures of 1.5dB or better at 10mW are achievable in the 1–2GHz range with 0.5μm technology, and improve with scaling.

/pdf/the-design-of-narrowband-cmos-rf-low-noise-amplifiers-4xu6d7na4v.pdf

The design of narrowband CMOS RF low-noise amplifiers

Summary form only given. Sensors add intelligence to systems which represent a broad class of devices incorporating functionalities like sensing, actuation, and control. They are the core of smart components and subsystems; then, the challenge in the realization of such smart systems goes beyond the design of the individual components and subsystems and consists of accommodating a multitude of functionalities, technologies, and materials to play a key role to augment our daily life.

Thomas H. Lee

Papers

Lumped, inductorless oscillators: how far can they go?

A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS

Effects of scaling on the SNR and speed of biosensors

The design of narrowband CMOS RF low-noise amplifiers

Terahertz electronics: The last frontier