There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

/pdf/differential-power-analysis-4t7fjmuc7b.pdf

Differential Power Analysis

N G van Kampen 1981 Amsterdam: North-Holland xiv + 419 pp price Dfl 180 This is a book which, at a lower price, could be expected to become an essential part of the library of every physical scientist concerned with problems involving fluctuations and stochastic processes, as well as those who just enjoy a beautifully written book. It provides an extensive graduate-level introduction which is clear, cautious, interesting and readable.

https://iopscience.iop.org/article/10.1088/0031-9112/34/4/040/pdf

Stochastic Processes in Physics and Chemistry

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

A new phase noise model was used to optimize a differential ring VCO for minimum power consumption. We compare the phase noise performance of three buffer stages using clamped, symmetric and cross-coupled loads, respectively. We propose a cross-coupled buffer topology that achieves lower phase noise by exploiting symmetry. Measured phase noise for a 1.2 mW, 150 MHz VCO fabricated in 0.5 /spl mu/m CMOS is -103.9 dBc/Hz at 500 kHz offset, showing good agreement with the theory.

CMOS VCOs for frequency synthesis in wireless biotelemetry

A 10/spl times/5 electrochemical biosensor array is designed and fabricated in standard 0.18 /spl mu/m CMOS. Each pixel occupies 160/spl times/120 /spl mu/m/sup 2/ and contains a programmable sensor capable of performing differential impedance spectroscopy, amperometric analysis, and field-effect sensing for molecular biology applications.

/pdf/a-programmable-electrochemical-biosensor-array-in-0-18-spl-48g8gf8iob.pdf

A programmable electrochemical biosensor array in 0.18 /spl mu/m standard CMOS

The first stage of a receiver is typically an LNA (low noise amplifier) which must provide sufficient gain while introducing as little noise as possible. Recently proposed noise optimization techniques for CMOS RF circuits permit greater flexibility in selection of device geometries as well as matching elements and biasing conditions to minimize the noise figure for a specified gain or power dissipation (Shaeffer and Lee, 1997). Nevertheless, such approaches still have ambiguity because intrinsic noise is assumed to be bias-independent. To utilize the new degrees of freedom in noise figure optimization, more complete intrinsic noise information on MOSFETs across the entire bias range is needed. A recent study has reported extensive experimental noise results of the 0.75 /spl mu/m SOI MOSFET technology (Dambrine et al, 1999) but provided limited guidance for actual LNA design. A physical noise simulator has been developed using two-dimensional device simulation; successful noise simulation results have been reported for MOSFETs with channel lengths down to 0.25 /spl mu/m for the first time (Goo et al, Proc. Symp. VLSI Tech., p. 153, 1999). Based on intrinsic high frequency noise simulation results, this paper presents explicit design guidelines for a CMOS tuned LNA with power constraints.

/pdf/guidelines-for-the-power-constrained-design-of-a-cmos-tuned-24957raff1.pdf

Guidelines for the power constrained design of a CMOS tuned LNA

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

We consider the problem of optimally allocating local feedback to the stages of a multistage amplifier. The local feedback gains affect many performance indices in a complicated and nonlinear fashion, making optimization of the feedback gains a very challenging problem. We show that geometric programming provides a complete solution.

/pdf/optimal-allocation-of-local-feedback-in-multistage-316qahmghx.pdf

Thomas H. Lee

Papers

CMOS VCOs for frequency synthesis in wireless biotelemetry

A programmable electrochemical biosensor array in 0.18 /spl mu/m standard CMOS

Guidelines for the power constrained design of a CMOS tuned LNA

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Optimal allocation of local feedback in multistage amplifiers via geometric programming