A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor Device and Method of Fabricating the Same

A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess having a rounded profile. A sidewall spacer is formed over the gate spacer and a sidewall of the recess. An insulating film is formed over the semiconductor substrate. The insulating film is selectively etched to form a landing plug contact hole. A conductive layer in the landing plug contact hole is filled to form a landing plug.

Semiconductor Device and Method for Fabricating the Same

This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

A Review on the ESD Robustness of Drain-Extended MOS Devices

A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.

Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication

In this work, the MPSCR structure have been verified in a 0.35-um 40-V CDMOS technology. The MPSCR structure with high ESD robustness has been clearly investigated by TLP instrument and TCAD simulator. By the simulation results, the modified P+ electrode layout of cathode side can enhance the turn-on efficiency of embedded SCR path, and avoid the current crowding effect on the surface of device. The proposed device only need to sweep N+ and P+ regions in drain side, and do not need to increase the additional mask layer. For area reduction, the MPSCR device does not need to increase the layout area and it can sustain up to 7.2kV for HBM and 360V for MM under device width of 300µm. Besides, the proposed MPSCR device has a low trigger voltage (Vt1=54-V) and a high second breakdown current (It2=10-A), which can be extensively applied for ESD protection design of PMIC applications.

The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Method of manufacturing fin diode structure

Lower trigger voltage ESD protection has been designed in PMIC application process. The proposed design lowers trigger voltage around 11% without extra mask layer and the layout diagram is simple and clear. The proposed device can be turned on quickly to protect the large array in output buffer design safely. It sustains 3.8kV human-body-model (HBM) and 350V machine model (MM) ESD tests, respectively.

Lower trigger voltage design for ESD protection device applied in PMIC application

A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

Tien-Hao Tang

Papers

The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

Method of manufacturing fin diode structure

Lower trigger voltage design for ESD protection device applied in PMIC application

Layout structure for electrostatic discharge protection