[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Integrated chip package structure using organic substrate and method of manufacturing the same

The Tektronix CT2 current probe is used to acquire more accurate Human Body Model waveforms with 0-ohm and 500 ohm tester loads than a CT1, owing to the CT2's low-frequency performance. The integrals and centroids of these waveforms then readily yield precise values of tester circuit elements and effective socket capacitance. Expressions are derived for effective socket capacitance resulting from distributed capacitance along a transmission line connecting to an unmatched load. These lead to options for reducing the effective socket capacitance while retaining the lines for delivering the HBM pulse.

http://ieeexplore.ieee.org/iel5/5611782/5623704/05623761.pdf

HBM tester waveforms, equivalent circuits, and socket capacitance

Analysis of cable discharge events (CDE) starts with the basic wire-to-ground pulse and continues, for shielded cables, with induced currents on the signal lines. These situations can be classified and analyzed through step response and impulse response. The essential behaviors can be derived from the uniformly charged shield being grounded to produce induced current on the data lines at the opposite end. This effect is called the W-pulse and is shown to be a kind of step response for both loads. From this and similar results, the effects on shielded cable lines of the commonly-applied IEC 61000-4-2 platform pulse are derived by convolution. Finally, the induced currents resulting from a charged shielded cable above a ground plane are deduced. Because the coupling from shielded cables to internal lines is almost all inductive, we have bipolar induced pulses with zero charge integral. Thus the bipolar data line response to these shielded cable pulses is a significant hazard for pulsed latchup. We discuss adequacy of the low-voltage IEC direct pin pulse (often called direct pin zap or DPZ) for assessing pulsed latchup on external ports, shielded in particular. Finally, it is shown why having connected cables as part of the regular IEC platform test also helps to test for cable discharge latchup hazards.

Primary and induced currents from cable discharges

CDM-like unipolar pulses are generated at the wafer level with excellent repeatability and linearity. Pulse width and rise time resemble that of FICDM testers. In-situ pre- and post-stress curve tracing reveals the current failure threshold for the device under test.

WCDM2 — Wafer-level charged device model testing with high repeatability

A circuit in accordance with the invention includes a resistive cpacitive timer (RC-timer), where the RC-timer includes circuitry to compensate for a leakage current through a capacitor in the RC timer.

Rc-timer scheme

Circuitry is provided which increases the efficiency of electrostatic discharge (ESD) power supply clamping circuitry to sink larger currents during an ESD event on a power supply node. Voltage clamp circuits capable of providing ESD protection to a supply node are described. The voltage clamp circuits include a discharge transistor which is controlled by a control circuit during an ESD event. The control circuit operates in response to a voltage provided on the protected supply node. One embodiment provides a P-channel MOS transistor and a control circuit which drives the gate of the transistor. Another embodiment provides an N-channel MOS transistor and a control circuit which drives the gate of the transistor.

Timothy J. Maloney

Papers

HBM tester waveforms, equivalent circuits, and socket capacitance

Primary and induced currents from cable discharges

WCDM2 — Wafer-level charged device model testing with high repeatability

Rc-timer scheme

Power supply clamp for esd protection