[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Integrated chip package structure using organic substrate and method of manufacturing the same

A field detection device such as a micro-strip portion of a transmission line may detect an electric field and a magnetic field induced by current steps injected into the chassis coupled to a ground plane The shield portions of the transmission line may be coupled to a first and a second port of an I/O connector A measurement system coupled to the connector may determine the electric field and the magnetic field detected by the micro-strip The measurement system may determine the electric field and magnetic field based on computing the sum and difference of the signals provided by the first port and the second port

Measuring electric and magnetic field

A method includes introducing into an integrated circuit a device comprising a transistor including a drain of a first conductivity type and a first concentration in a well of a first conductivity type and a second concentration, a first region of the first conductivity type and first concentration in the well, and a second region of a second conductivity type in the well between the first region and the drain The method also includes coupling the device to a pad In the presence of a pre-determined current at the pad, the device biases a junction between the second region and the well toward current flow in the absence of a latch-up event

Method for improved electrostatic discharge protection

This paper describes an ESD technology benchmarking strategy for evaluating the ESD robustness of a semiconductor technology. The strategy consists of a set of CMOS "building block" test structures, a matrix of these test structures, electrical characterization parameters, ESD metrics, a standardized failure criteria, and an extraction and testing procedure.

Electrostatic discharge (ESD) technology benchmarking strategy for evaluating ESD robustness of CMOS technologies

A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The wafer CDM (WCDM) pulses are accomplished with a probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.

Water-level charged device model for electrostatic discharge test methods, and apparatus using same

A handler simulator with a 50-ohm current detector creates CDM events for analysis and circuit modeling. The 50 ohms is mathematically removed to leave only air spark resistance, and the synthesized waveform, with higher peak current, is shown to relate to both CDM tester results and E-field in the factory.

http://ieeexplore.ieee.org/iel7/6959874/6968791/06968861.pdf

Timothy J. Maloney

Papers

Measuring electric and magnetic field

Method for improved electrostatic discharge protection

Electrostatic discharge (ESD) technology benchmarking strategy for evaluating ESD robustness of CMOS technologies

Water-level charged device model for electrostatic discharge test methods, and apparatus using same

Measuring handler CDM stress provides guidance for factory static controls