[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Integrated chip package structure using organic substrate and method of manufacturing the same

Lateral bipolar n/sup +/pn/sup +/ devices, with thick field oxide (TFO) separating the collector and emitter, are often used in snapback mode as protection devices for MOS ESD circuit protection. ESD testing for Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM) waveforms was performed on a family of TFO cells which varied the gate length (bipolar base width) as the experimental parameter. For MM and CDM, the data showed a dependence of withstand voltage on the gate length, indicating that longer gate lengths improve performance; while for HBM, withstand voltage was independent of the gate length. The devices exhibited failure modes that manifested as low level current leakage. Failure analysis identified the current leakage sites as melt filaments primarily localized at the TFO ends. Filament distribution was seen to be a function of gate length for MM. Two possible mechanisms are presented to account for the observed filament distribution and follow up experiments are suggested to test the validity of each.

Melt filaments in n + pn + lateral bipolar ESD protection devices

In some embodiments, a power supply clamp may include a switchable discharge device configured to discharge an electrostatic discharge; and a control circuit configured to generate a control voltage to turn off the discharge device at a shutoff time, with the shutoff time being long enough to allow the electrostatic discharge though the discharge device but short enough to reduce a duration of a power-up current transient through the discharge device. Other embodiments may be described and claimed.

Control circuit having a delay-reduced inverter

Apparatus and systems, as well as methods and articles, may operate to transmit an initial pulse to a directional coupler, where the initial pulse has an initial amplitude and a timed overshoot of a selected duration. Further activities may include stepping down the initial amplitude to an amplitude approximately equal to the initial amplitude times a mode reflection coefficient squared. A tuning stub may be coupled to a charge line to transmit the initial pulse, and decoupled from the charge line to refrain from receiving an echo pulse associated with the initial pulse.

Pulse transport apparatus, systems, and methods

A directional coupler can produce a z-matched square pulse, if a voltage step with overshoot of the correct magnitude and timing is used. Using an augmented transmission line to produce the overshoot, and strong coupling in the coupler, square pulses with high volts per charging volt and high return loss are demonstrated.

http://ieeexplore.ieee.org/iel5/5235855/5256743/05256766.pdf

Using coupled lines to produce highly efficient square pulses for VF-TLP

The feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) is extended to capture and simplify overall behavior of the metal. Of greatest interest to risk assessment is the peak temperature Tmax reached during an ESD event, and it is discovered that Tmax for Human Body and Charged Device Model (HBM, CDM) events follows its own simplified feedback equation with constant parameters. These constants are a function of the electrical and thermal properties of the metal layer. The result is a simple relation between Tmax and current density for the HBM or CDM event under consideration, a valuable aid to risk assessment and design rule checks. The summary equations capture the results of many detailed finite element and numerical convolution calculations of heat flow for on-chip metal.

http://ieeexplore.ieee.org/iel7/7565237/7574493/07574558.pdf

Timothy J. Maloney

Papers

Melt filaments in n + pn + lateral bipolar ESD protection devices

Control circuit having a delay-reduced inverter

Pulse transport apparatus, systems, and methods

Using coupled lines to produce highly efficient square pulses for VF-TLP

Modeling feedback effects in metal under ESD stress