Massive multiple-input multiple-output MIMO is one of themost promising technologies for the next generation of wirelesscommunication networks because it has the potential to providegame-changing improvements in spectral efficiency SE and energyefficiency EE. This monograph summarizes many years ofresearch insights in a clear and self-contained way and providesthe reader with the necessary knowledge and mathematical toolsto carry out independent research in this area. Starting froma rigorous definition of Massive MIMO, the monograph coversthe important aspects of channel estimation, SE, EE, hardwareefficiency HE, and various practical deployment considerations.From the beginning, a very general, yet tractable, canonical systemmodel with spatial channel correlation is introduced. This modelis used to realistically assess the SE and EE, and is later extendedto also include the impact of hardware impairments. Owing tothis rigorous modeling approach, a lot of classic "wisdom" aboutMassive MIMO, based on too simplistic system models, is shownto be questionable.

https://www.nowpublishers.com/article/DownloadSummary/SIG-093

Massive MIMO Networks: Spectral, Energy, and Hardware Efficiency

On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Complementary resistive switches for passive nanocrossbar memories

コンピュータ・サイエンス : ACM computing surveys

Digital Coding of Waveforms

This review focuses on electrochemical metallization memory cells (ECM), highlighting their advantages as the next generation memories. In a brief introduction, the basic switching mechanism of ECM cells is described and the historical development is sketched. In a second part, the full spectra of materials and material combinations used for memory device prototypes and for dedicated studies are presented. In a third part, the specific thermodynamics and kinetics of nanosized electrochemical cells are described. The overlapping of the space charge layers is found to be most relevant for the cell properties at rest. The major factors determining the functionality of the ECM cells are the electrode reaction and the transport kinetics. Depending on electrode and/or electrolyte material electron transfer, electro-crystallization or slow diffusion under strong electric fields can be rate determining. In the fourth part, the major device characteristics of ECM cells are explained. Emphasis is placed on switching speed, forming and SET/RESET voltage, R(ON) to R(OFF) ratio, endurance and retention, and scaling potentials. In the last part, circuit design aspects of ECM arrays are discussed, including the pros and cons of active and passive arrays. In the case of passive arrays, the fundamental sneak path problem is described and as well as a possible solution by two anti-serial (complementary) interconnected resistive switches per cell. Furthermore, the prospects of ECM with regard to further scalability and the ability for multi-bit data storage are addressed.

https://iopscience.iop.org/article/10.1088/0957-4484/22/25/254003/pdf

Electrochemical metallization memories—fundamentals, applications, prospects

As a possible successor for CMOS memory, hysteretic materials organized in crossbar structures are currently being investigated. Here, passive materials are of special importance as they maintain their functionality even when scaled down to the nanometer domain. With their regularity and inherent device density so-called nano-scaled crossbars seem to be very interesting for future components beyond the present scope of the ITRS-CMOS roadmap. But, due to their passive behavior they will not be capable of operating on their own without active devices that restore signal levels. This work investigates the limitations resistive hysteretic crossbars face due to their very nature and what performance CMOS read circuits will have to offer to let hybrid circuits result in a functional new technology.

Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory

In today's teaching and learning approaches for first-semester students, practical courses more and more often complement traditional theoretical lectures. This practical element allows an early insight into the real world of engineering, augments student motivation, and enables students to acquire soft skills early. This paper describes a new freshman introduction course into practical engineering, which has been established within the Bachelor of Science curriculum of Electrical Engineering and Information Technology of RWTH Aachen University, Germany. The course is organized as an eight-day, full-time block laboratory for over 300 freshman students, who were supervised by more than 60 tutors from 23 institutes of the Electrical Engineering Department. Based on a threefold learning concept comprising mathematical methods, MATLAB programming, and practical engineering, the students were required to transfer mathematical basics to algorithms in MATLAB in order to control LEGO Mindstorms robots. Toward this end, a new toolbox, called the ?RWTH-Mindstorms NXT Toolbox,? was developed, which enables the robots to be controlled remotely via MATLAB from a host computer. This paper describes how the laboratory course is organized and how it induces students to think as actual engineers would in solving real-world tasks with limited resources. Evaluation results show that the project improves the students' MATLAB programming skills, enhances motivation, and enables a peer learning process.

/pdf/matlab-meets-lego-mindstorms-a-freshman-introduction-course-1c3559j9xk.pdf

MATLAB Meets LEGO Mindstorms—A Freshman Introduction Course Into Practical Engineering

Nanoscale technology nodes bring reliability concerns back to the center stage of digital system design. A systematic classification of approaches that increase system resilience in the presence of functional hardware (HW)-induced errors is presented, dealing with higher system abstractions, such as the (micro)architecture, the mapping, and platform software (SW). The field is surveyed in a systematic way based on nonoverlapping categories, which add insight into the ongoing work by exposing similarities and differences. HW and SW solutions are discussed in a similar fashion so that interrelationships become apparent. The presented categories are illustrated by representative literature examples to illustrate their properties. Moreover, it is demonstrated how hybrid schemes can be decomposed into their primitive components.

/pdf/classification-of-resilience-techniques-against-functional-220sl43ync.pdf

Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems

The exploration of the design space for heterogeneous reconfigurable systems on chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks, ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Therefore, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions. A concept for a model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to prove the feasibility of this exploration strategy, first of all operations were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. Implementation parameters are provided for a variety of basic operations frequently required in digital signal processing. These implementation parameters serve as a basis for deriving models for the design space exploration concept.

Model-based exploration of the design space for heterogeneous systems on chip

The paper presents a high performance turbo decoder Its major building blocks, the maximum-a-posteriori decoder and the interleaver, are optimized from architecture to layout level to achieve high-throughput at low-power This includes a novel architecture for parallel interleaving, that sustains any interleaving scheme Moreover, the key features of the major building blocks are analyzed and modeled for quick design space exploration eg achieving 760 Mb/s at 570 mW in a 013 /spl mu/m-CMOS-technology Finally, the characterized implementations are benchmarked

Tobias G. Noll

Papers

Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory

MATLAB Meets LEGO Mindstorms—A Freshman Introduction Course Into Practical Engineering

Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems

Model-based exploration of the design space for heterogeneous systems on chip

A parametrizable low-power high-throughput turbo-decoder