The progressively decreasing feature size of the circuit components has tremendously increased the need for the global surface planarization of the various thin film layers that constitute the integrated circuit (IC). Global planarization, being one of the major solutions to meet the demands of the industry, needs to be achieved following the most efficient polishing procedure. Chemical mechanical polishing (CMP) is the planarization method that has been selected by the semiconductor industry today. CMP, an ancient process used for glass polishing, was adopted first as a microelectronic fabrication process by IBM in the 80 s for SiO2 polishing. To achieve efficient planarization at miniaturized device dimensions, there is a need for a better understanding of the physics, chemistry and the complex interplay of tribo-mechanical phenomena occurring at the interface of the pad and wafer in presence of the fluid slurry medium. In spite of the fact that CMP research has grown by leaps and bounds, there are some teething problems associated with CMP process such as delamination, microscratches, dishing, erosion, corrosion, inefficient post-CMP clean, etc.; research on which is still developing. The fundamental understanding of the CMP is highly necessary to characterize, optimize and model the process. The CMP process is ready to make a positive impact on 30% of the US$ 135 billion global semiconductor market. This paper presents an overview of CMP process in general, the science and mechanism of polishing, different metal and dielectric CMP processes. The impact of consumables on the CMP process, post-CMP cleaning, modeling of different CMP processes as well as the future trends are also discussed.

Chemical mechanical planarization for microelectronics applications

https://cyberleninka.org/article/n/1380904.pdf

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Papers

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