A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

This paper has presented a comprehensive overview of on-chip antennas, which remain the last bottleneck for achieving true SoC RF solutions. CMOS remains the mainstream IC technology choice but is not well suited for on-chip antennas, requiring the use of innovative design techniques to overcome its shortcomings. Codesign of circuits and antennas provide leverage to the designer to achieve optimum performance. The layout of on-chip antennas is dictated by foundry specific rules whereas characterization of on-chip antennas requires special text fixtures. For future highly integrated SoC solutions, foundries will have to provide special layers for efficient on-chip antenna implementations, as they currently do for on-chip inductors. In many of the emerging applications such as THz communication, implantable systems and energy harvesting, on-chip antennas have shown immense potential and are likely to play a major role in shaping up future communication systems.

The last barrier: on-chip antennas

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm2 while drawing 12 mA from 1.25 V supply.

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A Class-F CMOS Oscillator

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

In FDD cellular standards, the transmitter's out of-band noise leaks into the receive band due to the finite duplexer TX to RX isolation. If this noise is not low enough, a SAW filter is needed before the Power Amplifier to preserve the RX sensitivity. Out-of-band noise is also an important concern for coexistence of cellular transmitters with standards like GPS, WLAN and/or WiMAX on the same smart phone, a very common scenario nowadays. The SAW-less RX-band noise challenge becomes even more acute in the Long-Term Evolution (LTE) standard [1] where transmitters will need to operate in multiple FDD bands, using wider channel bandwidths and higher Peak-to-Average Power Ratios (PAPR).

A multiband LTE SAW-less modulator with −160dBc/Hz RX-band noise in 40nm LP CMOS

We present a multiband LTE SAW-less CMOS transmitter. Source followers, which drive passive mixers, contribute to the small-area and low-power transmitter. An envelope-tracking technique improves the linearity of RF programmable gain amplifiers, and Marchand baluns are suitable for multiband operation. The transmitter, which includes digital-to-analog converts and a phase-locked loop, covers 700 MHz to 2.6 GHz with −42 dBc ACLR. RX-band noise of −161 dBc/Hz is good enough for SAW-less operation.

A multiband LTE SAW-less CMOS transmitter with source-follower-drived passive mixers, envelope-tracked RF-PGAs, and Marchand baluns

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

We present a multiband LTE SAW-less CMOS transmitter. Source followers, which drive passive mixers, contribute to the small-area and low-power transmitter. An envelope-tracking technique improves the linearity of RF programmable gain amplifiers, and Marchand baluns are suitable for multiband operation. The transmitter, which includes digital-to-analog converts and a phase-locked loop, covers 700 MHz to 2.6 GHz with -42 dBc ACLR. RX-band noise of -161 dBc/Hz is good enough for SAW-less operation.

A Multiband LTE SAW-Less CMOS Transmitter with Source-Follower-Driven Passive Mixers, Envelope-Tracked RF-PGAs, and Marchand Baluns

A semiconductor device includes a filter circuit operable to pass a desired signal component of a high-frequency signal inputted and operable to attenuate a harmonic component of an integral multiple of the desired signal, wherein the filter circuit includes a first inductor and a second inductor coupled in series to a signal line transmitting the high-frequency signal, a first variable capacitor coupled between a power supply line and a node of the first inductor and the second inductor, and a second variable capacitor coupled between the signal line and the power supply line.

Tomohiro Sano

Papers

A multiband LTE SAW-less modulator with −160dBc/Hz RX-band noise in 40nm LP CMOS

A multiband LTE SAW-less CMOS transmitter with source-follower-drived passive mixers, envelope-tracked RF-PGAs, and Marchand baluns

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A Multiband LTE SAW-Less CMOS Transmitter with Source-Follower-Driven Passive Mixers, Envelope-Tracked RF-PGAs, and Marchand Baluns

Semiconductor device and adjustment method of filter circuit