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Design Of Analog Cmos Integrated Circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Silicon Photonics technology is rapidly maturing as a platform for larger-scale photonic circuits. As a result, the associated design methodologies are also evolving from componentoriented design to a more circuit-oriented design flow, that makes abstraction from the very detailed geometry and enables design on a larger scale. In this paper, we review the state of this emerging photonic circuit design flow and its synergies with electronic design automation (EDA). We cover the design flow from schematic capture, circuit simulation, layout and verification. We discuss the similarities and the differences between photonic and electronic design, and the challenges and opportunities that present themselves in the new photonic design landscape, such as variability analysis, photonic-electronic co-simulation and compact model definition. Silicon Photonics Circuit Design: Methods, Tools and

https://www.onlinelibrary.wiley.com/doi/epdf/10.1002/lpor.201700237

Silicon Photonics Circuit Design: Methods, Tools and Challenges

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm2 core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

A 2-mm $^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

A 0.25 /spl mu/m CMOS IC contains all analog and digital electronics required for a point-to-multipoint Bluetooth node. The circuit includes RF front-end and digital baseband processor, microprocessor and flash memory with software stack. The 41 mm/sup 2/ die has 15 dB noise figure and 2 dBm maximum transmitter output, and consumes 125 mW at 2.5 V during receive.

A fully-integrated single-chip SOC for Bluetooth

A key issue in the successful integration of analog circuits is a stable analog power supply. Traditional on-chip decoupling methods exhibit transients in the supply or voltage drops and power losses. This paper introduces the RLC decoupling method that features an enhanced transient response while being especially suited for low-power, low voltage applications. Both a theoretical and a practical approach are presented together with measurement results. As the benefits of a stable local power supply can be lost by the inadequate connection of two subcircuits with relative variations on the local grounds, a differential approach of signal transfer is proposed. Furthermore, the effect of a good local decoupling can be deteriorated by substrate noise, so some attention is given to this problem too.

Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 /spl mu/m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is 60 mA which allows a 155 Mb/s optical data-rate. The receiver is a three-stage transimpedance amplifier followed by a signal converter which provides digital output signal levels. The three-stage configuration makes possible the realization of a high transimpedance (150 k/spl Omega/), necessary to obtain a high sensitivity, combined with a high bandwidth. The achieved optical data-rate is 240 Mb/s for 1 /spl mu/A input modulation currents. This results in a transimpedance bandwidth of 18 THz/spl Omega/, which is one order of magnitude higher than recently published circuits. The speed performance of the total link is limited by the optical time-constant of the LED, leading to a 155 Mb/s optical link, designed for use in four-fiber interboard connections in 622 Mb/s B-ISDN systems. >

Mark Ingels

Papers

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

A 2-mm $^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

A fully-integrated single-chip SOC for Bluetooth

Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's

A CMOS 18 THz/spl Omega/ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links