http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

1. The real variable 2. Scalars and vectors 3. Tensors 4. Matrices 5. Multiple integrals 6. Potential theory 7. Operational methods 8. Physical applications of the operational method 9. Numerical methods 10. Calculus of variations 11. Functions of a complex variable 12. Contour integration and Bromwich's integral 13. Contour integration 14. Fourier's theorem 15. The factorial and related functions 16. Solution of linear differential equations of the second order 17. Asymptotic expansions 18. The equations of potential, waves and heat conduction 19. Waves in one dimension and waves with spherical symmetry 20. Conduction of heat in one and three dimensions 21. Bessel functions 22. Applications of Bessel functions 23. The confluent hypergeometric function 24. Legendre functions and associated functions 25. Elliptic functions Notes Appendix on notation Index.

Methods of Mathematical Physics. By Harold Jeffreys and Bertha Swirles Jeffreys. Pp. viii, 679. 63s. 1946. (Cambridge University Press)

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

In addition to the graphic-editing facilities, the software tool Tina proposes the construction of a number of representations for the behaviour of Petri nets or Time Petri nets. Various techniques are used to extract views of the behaviour of nets, preserving certain classes of properties of their state spaces. For Petri nets, these abstractions help prevent combinatorial explosion, relying on so-called partial order techniques such as covering steps and/or persistent sets. For Time Petri nets, which have, in general, infinite state spaces, they provide a finite symbolic representation of their behaviour in terms of state classes.

/pdf/the-tool-tina-construction-of-abstract-state-spaces-for-4y0s1f4zqq.pdf

The tool TINA – Construction of abstract state spaces for petri nets and time petri nets

Asynchronous Circuit Design

CTL model checking of time petri nets using geometric regions

System on a chip design results in the integration of digital, analog, and mixed-signal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDL-AMS to LHPNs. To support formal verification, this paper presents an efficient zone-based state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixed-signal circuit examples.

/pdf/verification-of-analog-mixed-signal-circuits-using-labeled-44bk51qcqn.pdf

Verification of analog/mixed-signal circuits using labeled hybrid petri nets

This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

Network-on-Chip (NoC) is now considered to be a promising approach to implementing many-core systems. In this paper, we propose fully asynchronous on-chip networks which have improved tolerance against stuck-at-faults, aging degradation faults and transient faults, as well as potential of high performance. We have developed a dependable routing algorithm to detour a faulty router or a faulty link based on local fault information. An adaptive routing algorithm based on local traffic load information is also used to achieve high performance. The proposed router circuits are based on the bundled-data method with MOUSETRAP-like transition signaling protocol, where programmable delay elements for the matched delays are used in order to tolerate static and dynamic delay variations. Duplicated control circuits for tolerating transient faults are also designed and evaluated. The LEDR (Level Encoded Dual Rail) encoding method is used in the link implementation to avoid the resetting phase overhead. The proposed on-chip networks are implemented using 130nm process technology for checking the correct functionality and evaluating performance.

Improving Dependability and Performance of Fully Asynchronous On-chip Networks

This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthesis is used to allow for global and timing optimization. In order to reduce the overhead in resetting phases, a protocol called early acknowledgment protocol and its STG (signal transition graph) generation technique are proposed. In this protocol, the state variables inserted to guarantee that STGs have CSC (complete state coding) usually cause no overhead. The experiments to synthesize a portion of a DCT circuit show that the proposed method can handle a nontrivial example and produce a smaller and faster circuit than a previous approach.

Tomohiro Yoneda

Papers

CTL model checking of time petri nets using geometric regions

Verification of analog/mixed-signal circuits using labeled hybrid petri nets

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

Improving Dependability and Performance of Fully Asynchronous On-chip Networks

High level synthesis of timed asynchronous circuits