Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

Metal–Oxide RRAM

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory

This review article attempts to provide a comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) First, a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMs over the past decade Second, both inorganic and organic materials used in RRAMs are summarized, and their respective advantages and shortcomings are discussed Third, the important switching mechanisms are discussed in depth and are classified into ion migration, charge trapping/de-trapping, thermochemical reaction, exclusive mechanisms in inorganics, and exclusive mechanisms in organics Fourth, attention is given to the application of RRAMs for data storage, including their current performance, methods for performance enhancement, sneak-path issue and possible solutions, and demonstrations of 2-D and 3-D crossbar arrays Fifth, prospective applications of RRAMs in unconventional computing, as well as logic devices and multi-functionalization of RRAMs, are comprehensively summarized and thoroughly discussed The present review article ends with a short discussion concerning the challenges and future prospects of the RRAMs

Recent progress in resistive random access memories: Materials, switching mechanisms, and performance

Nonvolatile memories with fast write operation at low voltage are required as storage devices to exceed flash memory performance [1–3]. We develop an 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput (64b parallel write per 17.2ns cycle), which is almost twice as fast as existing methods, using the fast-switching performance of TaO x ReRAM [4] and the following three techniques to reduce the sneak current in bipolar type cross-point cell array structure in an 0.18μm process. First, memory cell and array technologies reduce the sneak current with a newly developed bidirectional diode as a memory cell select element for the first time. Second, we use a hierarchical bitline (BL) structure for multi-layered cross-point memory with fast and stable current control. Third, we implement a multi-bit write architecture that realizes fast write operation and suppresses sneak current. This work is applicable to both high-density stand-alone and embedded memory with more stacked memory arrays and/or scaling memory cells.

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

There is provided a semiconductor memory device in which a bit line precharge operation is increased in speed, and a layout area is reduced. P-channel transistors ( 206, 207 ) that function as switches are provided in a precharge voltage pumping circuit ( 105 ) included in a bit line precharge voltage generation unit. This enhances a pumping efficiency, and reduces a capacitance area of a pumping capacitor ( 200 ).

Semiconductor memory device, and semiconductor device with the semiconductor memory device and logic circuit device therein

PROBLEM TO BE SOLVED: To solve the problem that the number of mounted chip regions obtained from one semiconductor wafer is limited and it becomes an obstacle for reducing the cost of LSI since an inspection circuit region and the mounted chip region being the object for inspection are arranged on a semiconductor wafer in a pair in a conventional case. SOLUTION: Chip region selection circuits 209 and 210 and a chip region selection signal input terminal 208 are disposed in the inspection circuit region 206 on the semiconductor wafer. Thus, one inspection circuit region 206 can be shared by the two mounted chip regions 201 and 202. Consequently, the number of the inspection circuit regions arranged on one semiconductor wafer can remarkably be reduced, and therefore the number of the mounted chip regions obtained from one semiconductor wafer can be increased.

Method of manufacturing semiconductor integrated circuit and semiconductor device

A power generation block configured to generate internal power by a charge pump circuit and a power supply control block configured to control the power generation block are provided. First and second power supply interconnects individually separated from an external power supply interconnect are connected to the power generation block and the power supply control block, respectively. At least any one of the power supply interconnects is provided with a filter section configured to remove noise propagating through the power supply interconnect.

Semicondcutor integrated circuit including power generation block and power supply control block

There is provided a semiconductor memory device in which a bit line precharge operation is increased in speed, and a layout area is reduced. P-channel transistors (206, 207) that function as switchesare provided in a precharge voltage pumping circuit (105) included in a bit line precharge voltage generation unit. This enhances a pumping efficiency, and reduces a capacitance area of a pumping capacitor (200).

Toshihiro Nakamura

Papers

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

Semiconductor memory device, and semiconductor device with the semiconductor memory device and logic circuit device therein

Method of manufacturing semiconductor integrated circuit and semiconductor device

Semicondcutor integrated circuit including power generation block and power supply control block

Semiconductor memory device and semiconductor device carried with the same and logic circuit device