Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

The organization of behavior: A neuropsychological theory

Recent advances in physical reservoir computing: A review

Spintronic devices exploit the spin, as well as the charge, of electrons and could bring new capabilities to the microelectronics industry However, in order for spintronic devices to meet the ever-increasing demands of the industry, innovation in terms of materials, processes and circuits are required Here, we review recent developments in spintronics that could soon have an impact on the microelectronics and information technology industry We highlight and explore four key areas: magnetic memories, magnetic sensors, radio-frequency and microwave devices, and logic and non-Boolean devices We also discuss the challenges—at both the device and the system level—that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms This Review Article examines the potential of spintronics in four key areas of application —memories, sensors, microwave devices, and logic devices — and discusses the challenges that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms

Opportunities and challenges for spintronics in the microelectronics industry

Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 µW at 10 MHz using 0.13 µm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 µW, respectively.

/pdf/an-optimized-s-box-circuit-architecture-for-low-power-aes-b9hmw9k547.pdf

An Optimized S-Box Circuit Architecture for Low Power AES Design

To implement job execution in which resource assignment and change of the assignment can be dynamically and autonomously performed so as to meet requirements of a job in a job and resource environment in which the operational status cannot be forecasted in advance. A job that can be divided into a selected number of tasks is provided to one computer of a plurality of computers connected via networks, and job tasks are processed with the one computer for predetermined time. A progress rate of task processing for the predetermined time is calculated, and completion time for task processing on the one computer is estimated on the basis of the progress rate and the predetermined time. It is determined whether the estimated completion time meets requirements of the job. When the estimated completion time meets the requirements, job tasks are processed with the one computer, and results are generated. When the estimated completion time does not meet the requirements, job tasks are divided into tasks to be left on the one computer and tasks to be transferred to another computer. The left job tasks are processed with the one computer for further predetermined time, and simultaneously, the tasks to be transferred are transferred to the other computer and the other computer is caused to process the transferred tasks.

Job execution method, job execution system, and job execution program

Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object. An anomaly detecting method includes: sequentially generating directional data indicating a feature of each piece of monitored data correspondingly to the monitored data which are input in sequence; calculating the dissimilarity of the directional data to a reference vector; updating a moment of the distribution of the dissimilarity appearing when the directional data is modeled with a multi-dimensional probability distribution, based on the moment already corresponding to the monitored data; calculating a parameter determining the variance of the multi-dimensional probability distribution, on the basis of the moment; calculating a threshold of the dissimilarity on the basis of the multi-dimensional probability distribution the variance of which is determined by the parameter; and detecting an anomaly in the monitored data that corresponds to the dissimilarity if the dissimilarity exceeds the threshold.

Anomaly detection based on directional data

This paper deals with mm Wave MIMO link design strategy for wireless data center applications where the MIMO degrees of freedom is taken into account in multi-node packet networking environments. The problem is treated differently from the coordinated multiuser MIMO situation and the link design is optimized independently in each node with meeting control and data plane requirements for contention-based packet switching. In particular, we propose using an interference-aligned out-of-band control plane to improve the unidirectional bonded in-band data plane collision-related performance degradation with a limited number of antenna elements per node. We also present a high-level implementation plan.

MIMO link design strategy for wireless data center applications

The development of hardware neural networks, including neuromorphic hardware, has been accelerated over the past few years. However, it is challenging to operate very large-scale neural networks with low-power hardware devices, partly due to signal transmissions through a massive number of interconnections. Our aim is to deal with the issue of communication cost from an algorithmic viewpoint and study learning algorithms for energy-efficient information processing. Here, we consider two approaches to finding spatially arranged sparse recurrent neural networks with the high cost-performance ratio for associative memory. In the first approach following classical methods, we focus on sparse modular network structures inspired by biological brain networks and examine their storage capacity under an iterative learning rule. We show that incorporating long-range intermodule connections into purely modular networks can enhance the cost-performance ratio. In the second approach, we formulate for the first time an optimization problem where the network sparsity is maximized under the constraints imposed by a pattern embedding condition. We show that there is a tradeoff between the interconnection cost and the computational performance in the optimized networks. We demonstrate that the optimized networks can achieve a better cost-performance ratio compared with those considered in the first approach. We show the effectiveness of the optimization approach mainly using binary patterns and apply it also to gray-scale image restoration. Our results suggest that the presented approaches are useful in seeking more sparse and less costly connectivity of neural networks for the enhancement of energy efficiency in hardware neural networks.

/pdf/spatially-arranged-sparse-recurrent-neural-networks-for-455ta2gwy1.pdf

Toshiyuki Yamane

Papers

Recent advances in physical reservoir computing: A review

Job execution method, job execution system, and job execution program

Anomaly detection based on directional data

MIMO link design strategy for wireless data center applications

Spatially Arranged Sparse Recurrent Neural Networks for Energy Efficient Associative Memory