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Uzi Vishkin

Researcher at University of Maryland, College Park

Publications -  224
Citations -  12006

Uzi Vishkin is an academic researcher from University of Maryland, College Park. The author has contributed to research in topics: Parallel algorithm & Compiler. The author has an hindex of 57, co-authored 219 publications receiving 11690 citations. Previous affiliations of Uzi Vishkin include Max Planck Society & Tel Aviv University.

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Proceedings ArticleDOI

Can parallel algorithms enhance serial implementation

TL;DR: The broad thesis presented suggests that the serial emulation of a parallel algorithm has the potential advantage of running an a serial machine faster than a standard serial algorithm for the same problem.
Patent

Circuit architecture for reduced-synchrony on-chip interconnect

TL;DR: In this article, an interconnect is proposed for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers.
Book

Structural parallel algorithmics

Uzi Vishkin
TL;DR: The first half of the paper is a general introduction which emphasizes the central role that the PRAM model of parallel computation plays in algorithmic studies for parallel computers as mentioned in this paper, and the second half is a summary of the main points of this paper.
Proceedings Article

On a Parallel-Algorithms Method for String Matching Problems.

TL;DR: In this article, the authors show how to break symmetries that occur in the process of assigning labels using the Deterministic Coin Tossing (DCT) technique, and thereby reduce the number of labeled substrings to linear.
Patent

Optical interconnect structure in a computer system and method of transporting data between processing elements and memory through the optical interconnect structure

TL;DR: In this paper, a multi-chip processor/memory arrangement replacing a large computer chip, including a number of modules each including processing elements, registers and/or memories interconnected by an optical interconnection fabric providing an all-to-all interconnection between the chips, so that the memory cells on each chip represent a portion of shared memory.