Covering the basic techniques used in the latest research work, the author consolidates progress made so far, including some very recent and promising results, and conveys the beauty and excitement of work in the field. He gives clear, lucid explanations of key results and ideas, with intuitive proofs, and provides critical examples and numerous illustrations to help elucidate the algorithms. Many of the results presented have been simplified and new insights provided. Of interest to theoretical computer scientists, operations researchers, and discrete mathematicians.

Approximation Algorithms

The success of the von Neumann model of sequential computation is attributable to the fact that it is an efficient bridge between software and hardware: high-level languages can be efficiently compiled on to this model; yet it can be effeciently implemented in hardware. The author argues that an analogous bridge between software and hardware in required for parallel computation if that is to become as widely used. This article introduces the bulk-synchronous parallel (BSP) model as a candidate for this role, and gives results quantifying its efficiency both in implementing high-level language features and algorithms, as well as in being implemented in hardware.

A bridging model for parallel computation

We survey the current techniques to cope with the problem of string matching that allows errors. This is becoming a more and more relevant issue for many fast growing areas such as information retrieval and computational biology. We focus on online searching and mostly on edit distance, explaining the problem and its relevance, its statistical behavior, its history and current developments, and the central ideas of the algorithms and their complexities. We present a number of experiments to compare the performance of the different algorithms and show which are the best choices. We conclude with some directions for future work and open problems.

/pdf/a-guided-tour-to-approximate-string-matching-22fowlmq5b.pdf

A guided tour to approximate string matching

An edited volume containing data structures and algorithms for information retrieved including a disk with examples written in C. For programmers and students interested in parsing text, automated indexing, its the first collection in book form of the basic data structures and algorithms that are critical to the storage and retrieval of documents.

https://hornad.fei.tuke.sk/~genci/Vyucba/OOBDS/Archiv/Podklady/TExtoveIS&IR/Information%20Retrieval%20Data%20Structures%20&%20Algorithms.PDF

Information Retrieval: Data Structures and Algorithms

Often, in the real world, entities have two or more representations in databases. Duplicate records do not share a common key and/or they contain errors that make duplicate matching a difficult task. Errors are introduced as the result of transcription errors, incomplete information, lack of standard formats, or any combination of these factors. In this paper, we present a thorough analysis of the literature on duplicate record detection. We cover similarity metrics that are commonly used to detect similar field entries, and we present an extensive set of duplicate detection algorithms that can detect approximately duplicate records in a database. We also cover multiple techniques for improving the efficiency and scalability of approximate duplicate detection algorithms. We conclude with coverage of existing tools and with a brief discussion of the big open problems in the area

/pdf/duplicate-record-detection-a-survey-4crkywvv1d.pdf

Duplicate Record Detection: A Survey

Oblivious RAM (ORAM) is a cryptographic primitive that allows a trusted CPU to securely access untrusted memory, such that the access patterns reveal nothing about sensitive data. ORAM is known to have broad applications in secure processor design and secure multiparty computation for big data. Unfortunately, due to a logarithmic lower bound by Goldreich and Ostrovsky (J ACM 43(3):431–473, 1996), ORAM is bound to incur a moderate cost in practice. In particular, with the latest developments in ORAM constructions, we are quickly approaching this limit, and the room for performance improvement is small. In this paper, we consider new models of computation in which the cost of obliviousness can be fundamentally reduced in comparison with the standard ORAM model. We propose the oblivious network RAM model of computation, where a CPU communicates with multiple memory banks, such that the adversary observes only which bank the CPU is communicating with, but not the address offset within each memory bank. In other words, obliviousness within each bank comes for free—either because the architecture prevents a malicious party from observing the address accessed within a bank, or because another solution is used to obfuscate memory accesses within each bank—and hence we only need to obfuscate communication patterns between the CPU and the memory banks. We present new constructions for obliviously simulating general or parallel programs in the network RAM model. We describe applications of our new model in distributed storage applications with a network adversary.

/pdf/oblivious-network-ram-and-leveraging-parallelism-to-achieve-1gyp6k8qyd.pdf

Oblivious Network RAM and Leveraging Parallelism to Achieve Obliviousness

A multi-chip processor/memory arrangement (20) is shown which includes a plurality of modules (22), also referred to herein as chips. The modules (22) are interconnected there between by an optical interconnect structure (24) also referred to herein as optical interconnect fabric. The basic concept underlining the structure of the arrangement (20) is to position the processing elements and memory cells on the small chips (22) which are fabricated in mass production based on inexpensive technology, for example, 0.25 micron technology and interconnected with the optical interconnect fabric (24). Packaged with the optical interconnect structure (24), a plurality of inexpensive chips (22) provides sufficient performance but for a small fraction of the cost of the processor/memory argument implemented on a single large computer chips (0.065 micron chip).

Optical interconnect structure in a computer system

Providing undergraduate students with an opportunity to ex perience meaningful academic research has a potential impact on their future career choic e. Our approach combines two seemingly contradicting attributes: (i) to make it excitin g, the effort targets a grand research objective; and (ii) to make the experience self-assuring an d overall positive, the concrete task handed to a student is feasible, given their background and t ime constraints, while still contributing towards the grand objective. We believe that t is can motivate a wider range of undergraduate students, including underrepresented grou ps of undergraduate engineering students to pursue an engineering career path, academic or otherwise . In this paper, we describe a pilot of an on-going, multiple-y ear research project, carried out by undergraduate female students incorporating research and education in computer science and engineering (CS&E). Many-core processors are becoming inc reasingly popular in general-purpose computing. While most researchers agree t hat this requires introduction of parallelism to mainstream CS&E practice, and hence educati on, parallel programming difficulties remain obstacles that are yet to be overcome. For concretene ss, th research project involves a certain many-core framework, called eXplicit Multi-Threa ding (XMT). The XMT framework provides a general-purpose many-core architecture for fine -grained parallel programs that scales to a thousand lightweight cores, aiming to improve single ta sk execution time through parallelism. What makes XMT attractive is that it has been su pported by significant evidence on ease-of-programming and competitive performance. The XMT platform consists of a proof-of-concept 64-core FPGA and ASIC prototypes and a hig hly configurable cycle-accurate simulator (XMTSim), capable of modeling a target 1024-core XMT. Our work aims to parallelize XMTSim. (i) The grand objective s to establish that XMT is an effective self-simulating machine; namely, to efficiently simulate the XMTSim code by XMTSim itself. What makes this objective grand, and therefore insp iring, is that one of the elegant features of Turing machines was their ability to provide self-simula tions. This feature has been used in support of the thesis that Turing machines are general-purp ose. (ii) The combined milestone for the student projects is parallelizing the most computation lly time-consuming component of XMTSim, the Interconnection Network (ICN) of XMT. (iii) Eac h student is being given a part of the job. Introduction Research opportunities for undergraduate students are bec oming more common, and undergraduate students often expect to experience academi c r search before they graduate. Moreover, a positive and meaningful experience with engine eri g research contributes to the motivation of these students to pursue a future career in eng in ering and computer science, whether in graduate school or industry. Yet, finding ways of i nvolving undergraduate students in active research introduces many challenges (e.g. [4]). Fur thermore, ensuring that the research experience benefits the students as well as advances the rese arch is an even greater challenge. Our research involves parallel computing in the form of many -core processors. In order for an existing program’s performance to improve with new generat ions of multiprocessors, the program needs to be parallelized. However, extracting parallelism fro a serial task, and parallel programming in general, is a major challenge to the software industry and anyone using computers [5]. The undergraduate students that are involved in our researc h h ve limited time to dedicate to research, and usually come with little preparation. These f actors add to the inherent complexities of parallel programing. The eXplicit Multi-Threading (XMT ) general-purpose many-core platform for fine grained parallel programs makes an attract ive framework given the above challenges. XMT is easy to teach, facilitating a smoother le arning curve for students that are new to parallel programming and have limited background in para llel rchitectures [9]. In this work, we aim to parallelize the cycle-accurate simul ator of XMT, XMTSim, with the following goals: 1. Establish that XMT is an effective self simulating machin e; amely simulating efficiently the XMTSim code by XMTSim itself. 2. Parallelize the most computationally time-consuming co mp nent of the simulation, the Interconnection Network (ICN). 3. Carving out the parallelization task into small projects suitable for a single undergraduate student to pursue in one summer. This paper presents a pilot study intended to reinforce the c laim that XMT is easy to teach, by demonstrating that the students were able to learn to parall el program well enough to advance our research goal within the limited time scope. Our preliminar y results already show that parallelizing the ICN obtains simulation speedups of x54 co mpared to the best serial implementation on a 64-core XMT. A large factor that enabled us to achieve this goal was breaking down the project into smaller, more manageable com ponents. Computer engineering and science is underrepresented by ce rtain groups, mainly women and minorities. There is an increasing effort to attract these g roups, with one example being DREU: distributed research experience for undergraduates from u nderrepresented groups [3]. We believe that XMT makes for a good medium to attract these groups, or to retain them in the field. The XMT Many-core Platform The primary goal of the eXplicit Multi-Threading (XMT) gene ral-purpose computer architecture [10] has been improving single-task performa nce through parallelism. XMT was designed from the ground up to capitalize on the huge on-chip resources becoming available in order to support the formidable body of knowledge, known as P arallel Random Access Model (PRAM) algorithmics [7], and the latent, though not widespr ead, familiarity with it. Driven by the repeated programming difficulties of parallel machines, ea e-of-programming was a leading design objective of XMT. The XMT architecture, depicted in Figure 1, includes an arra y of lightweight cores, Thread Control Units (TCUs), and a serial core with its own cache (Ma ster TCU). The architecture includes several clusters of TCUs connected to mutually-ex clusive shared cache modules by a highly optimized interconnection network [1]. XMT does not feature writable private caches except for the Master TCU. Moreover, since the cache modules are mutually exclusive, no cache coherence is required. TCUs include lightweight ALUs, but t he more heavy-weight units are shared by all TCUs in a cluster. XMT is programmed in XMTC, a si mple extension of the C language which contains succession of serial and parallel c ode sections. The code of a parallel section is expressed in the SPMD (single program, multiple d ata) style, specifying an arbitrary number of virtual threads sharing the same code. Further det ails on the XMT architecture can be found in [10]. Global Register File Prefix-Sum Unit

/pdf/ac-2012-3055-parallel-simulation-of-many-core-proces-sors-2o083injdl.pdf

Ac 2012-3055: parallel simulation of many-core proces- sors: integration of research and education

Human immunoglobulin heavy chain (IGH) locus on chromosome 14 includes more than 40 functional copies of the variable gene (IGHV), which are critical for the structure of antibodies that identify and neutralize pathogenic invaders as a part of the adaptive immune system. Because of its highly repetitive sequence composition, the IGH locus has been particularly difficult to assemble or genotype when using standard short-read sequencing technologies. Here, we introduce ImmunoTyper-SR, an algorithmic tool for the genotyping and CNV analysis of the germline IGHV genes on Illumina whole-genome sequencing (WGS) data using a combinatorial optimization formulation that resolves ambiguous read mappings. We have validated ImmunoTyper-SR on 12 individuals, whose IGHV allele composition had been independently validated, as well as concordance between WGS replicates from nine individuals. We then applied ImmunoTyper-SR on 585 COVID patients to investigate the associations between IGHV alleles and anti-type I IFN autoantibodies, which were previously associated with COVID-19 severity. 

ImmunoTyper-SR: A computational approach for genotyping immunoglobulin heavy chain variable genes using short-read data.

An abstract of this work will be presented at the Compiler, Architecture and Tools Conference (CATC), Intel Development Center, Haifa, Israel November 23, 2015.

Uzi Vishkin

Papers

Oblivious Network RAM and Leveraging Parallelism to Achieve Obliviousness

Optical interconnect structure in a computer system

Ac 2012-3055: parallel simulation of many-core proces- sors: integration of research and education

ImmunoTyper-SR: A computational approach for genotyping immunoglobulin heavy chain variable genes using short-read data.

Can Cooling Technology Save Many-Core Parallel Programming from Its Programming Woes?