Covering the basic techniques used in the latest research work, the author consolidates progress made so far, including some very recent and promising results, and conveys the beauty and excitement of work in the field. He gives clear, lucid explanations of key results and ideas, with intuitive proofs, and provides critical examples and numerous illustrations to help elucidate the algorithms. Many of the results presented have been simplified and new insights provided. Of interest to theoretical computer scientists, operations researchers, and discrete mathematicians.

Approximation Algorithms

The success of the von Neumann model of sequential computation is attributable to the fact that it is an efficient bridge between software and hardware: high-level languages can be efficiently compiled on to this model; yet it can be effeciently implemented in hardware. The author argues that an analogous bridge between software and hardware in required for parallel computation if that is to become as widely used. This article introduces the bulk-synchronous parallel (BSP) model as a candidate for this role, and gives results quantifying its efficiency both in implementing high-level language features and algorithms, as well as in being implemented in hardware.

A bridging model for parallel computation

We survey the current techniques to cope with the problem of string matching that allows errors. This is becoming a more and more relevant issue for many fast growing areas such as information retrieval and computational biology. We focus on online searching and mostly on edit distance, explaining the problem and its relevance, its statistical behavior, its history and current developments, and the central ideas of the algorithms and their complexities. We present a number of experiments to compare the performance of the different algorithms and show which are the best choices. We conclude with some directions for future work and open problems.

/pdf/a-guided-tour-to-approximate-string-matching-22fowlmq5b.pdf

A guided tour to approximate string matching

An edited volume containing data structures and algorithms for information retrieved including a disk with examples written in C. For programmers and students interested in parsing text, automated indexing, its the first collection in book form of the basic data structures and algorithms that are critical to the storage and retrieval of documents.

https://hornad.fei.tuke.sk/~genci/Vyucba/OOBDS/Archiv/Podklady/TExtoveIS&IR/Information%20Retrieval%20Data%20Structures%20&%20Algorithms.PDF

Information Retrieval: Data Structures and Algorithms

Often, in the real world, entities have two or more representations in databases. Duplicate records do not share a common key and/or they contain errors that make duplicate matching a difficult task. Errors are introduced as the result of transcription errors, incomplete information, lack of standard formats, or any combination of these factors. In this paper, we present a thorough analysis of the literature on duplicate record detection. We cover similarity metrics that are commonly used to detect similar field entries, and we present an extensive set of duplicate detection algorithms that can detect approximately duplicate records in a database. We also cover multiple techniques for improving the efficiency and scalability of approximate duplicate detection algorithms. We conclude with coverage of existing tools and with a brief discussion of the big open problems in the area

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Duplicate Record Detection: A Survey

Faced with nearly stagnant clock speed advances, chip manufacturers have turned to parallelism as the source for continuing performance improvements. But even though numerous parallel architectures have already been brought to market, a universally accepted methodology for programming them for general purpose applications has yet to emerge. Existing solutions tend to be hardware-specific, rendering them difficult to use for the majority of application programmers and domain experts, and not providing scalability guarantees for future generations of the hardware. 
This dissertation advances the validation of the following thesis: it is possible to develop efficient general-purpose programs for a many-core platform using a model recognized for its simplicity. To prove this thesis, we refer to the eXplicit Multi-Threading (XMT) architecture designed and built at the University of Maryland. XMT is an attempt at re-inventing parallel computing with a solid theoretical foundation and an aggressive scalable design. Algorithmically, XMT is inspired by the PRAM (Parallel Random Access Machine) model and the architecture design is focused on reducing inter-task communication and synchronization overheads and providing an easy-to-program parallel model. 
This thesis builds upon the existing XMT infrastructure to improve support for efficient execution with a focus on ease-of-programming. Our contributions aim at reducing the programmer's effort in developing XMT applications and improving the overall performance. More concretely, we: (1) present a work-flow guiding programmers to produce efficient parallel solutions starting from a high-level problem; (2) introduce an analytical performance model for XMT programs and provide a methodology to project running time from an implementation; (3) propose and evaluate RAP—an improved resource-aware compiler loop prefetching algorithm targeted at fine-grained many-core architectures; we demonstrate performance improvements of up to 34.79% on average over the GCC loop prefetching implementation and up to 24.61% on average over a simple hardware prefetching scheme; and (4) implement a number of parallel benchmarks and evaluate the overall performance of XMT relative to existing serial and parallel solutions, showing speedups of up to 13.89x vs. a serial processor and 8.10x vs. parallel code optimized for an existing many-core (GPU). We also discuss the implementation and optimization of the Max-Flow algorithm on XMT, a problem which is among the more advanced in terms of complexity, benchmarking and research interest in the parallel algorithms community. We demonstrate better speed-ups compared to a best serial solution than previous attempts on other parallel platforms.

Optimizing for a many-core architecture without compromising ease-of-programming

Consider algorithms which are designed for shared memory models of parallel computation in which processors are allowed to have fairly unrestricted access patterns to the shared memory. General fast simulations of such algorithms by parallel machines in which the shared memory is organized in modules where only one cell of each module can be accessed at a time are proposed. The paper provides a comprehensive study of the problem. The solution involves three stages:
(a) Before a simulation, distribute randomly the memory addresses among the memory modules.
(b) Keep several copies of each address and assign memory requests of processors to the "right'; copies at any time.
(c) Satisfy these assigned memory requests according to specifications of the parallel machine.

/pdf/granularity-of-parallel-memories-4pificlku2.pdf

Granularity of Parallel Memories

In this paper, we present the work in progress that studies the run-time impact of various DTM techniques on a proposed 1024-core XMT chip. XMT aims to improve single task performance using fine-grained parallelism. Via simulations, we show that relative to a general global scheme, speedups of up to 46% with a dedicated interconnection controller and 22% with distributed control of computing clusters are possible. Our findings lead to several high level insights that can impact the design of a broader family of shared memory many-core systems.

/pdf/thermal-management-of-a-many-core-processor-under-fine-941m8o5y5q.pdf

Thermal management of a many-core processor under fine-grained parallelism

In this technical report, we present information on the XMTC compiler and language. We start by presenting the XMTC Memory Model and the issues we encountered when using GCC, the popular GNU compiler for C and other sequential languages, as the basis for a compiler for XMTC, a parallel language. These topics, along with some information on XMT specic optimizations were presented in (10). Then, we proceed to give some more details on how outer spawn statements (i.e., parallel loops) are compiled to take advantage of XMT's unique hardware primitives for scheduling at parallelism and how we incremented this basic compiler to support nested parallelism.

/pdf/the-compiler-for-the-xmtc-parallel-language-lessons-for-4wu1eqiypb.pdf

The compiler for the XMTC parallel language: Lessons for compiler developers and in-depth description

Explicit Multi-Threading (XMT) is a fine-grained computation framework introduced in our SPAA‘98 paper. XMT aims at faster single-task completion time by way of instruction-level parallelism (ILP). Building on some key ideas from parallel computing, XMT covers the spectrum from algorithms through architecture to implementation; the main implementation related innovation in XMT was through the incorporation of low-overhead hardware mechanisms (for more effective fine-grained parallelism). If and when implemented, XMT will enable the algorithm designer and the programmer to reason about parallel algorithms in a very simple parallel computation model, known as the PRAM (for parallel random-access-machine). The algorithmdtheory community has developed PRAM algorithmics during the past two decades to the level where it appears to be second in magnitude only to serial algorithmics. Many elegant techniques and paradigms have been introduced. However, the evolution of multiprocessors never reached a situation where the PRAM model offered effective abstraction for them. So, this elegant theory has not been matched by an experimental study of what works better. more refined performance measurements, and a broad study of applications. In particular, the general question “how good parallel algorithms can really be” remained generally open. A year 2000 perspective is that: Through XMT, the upcoming “on-chip Billion transistor” era calls for a massive revisit of PRAM-related algorithmics. “PRAM-on-chip’’ is an original direction for addressing the fascinating question: What to do with all the on-chip hardware once the returns on adding more on-chip memory start to diminish? This direction is the main innovation of XMT. A few pointed examples of PRAM revisits will be provided. Although a good first step, there is much more to do beyond just examining previous approaches and get the most practical algorithm out of them. The examples will demonstrate: (i) Understanding the profound differences between XMT and more traditional parallel computing implementation platforms/models. (ii) Seeking good speedups for bounded size inputs. (iii) Incorporating rigorous non-asymptotic performance analysis into experimental performance analysis. (iv) Providing examples where experimental research and theoretical analysis complement one another. Work in progress includes, studying major application domains, compiler and system-related work, as well as VLSI-related work. Overall, XMT provides ample research opportunities through mixing theory and experimentation. The XMT home page is at: http://www.umiacs.umd.edu/ vishkin/XMT

http://ieeexplore.ieee.org/iel5/7055/19010/00878204.pdf

Uzi Vishkin

Papers

Optimizing for a many-core architecture without compromising ease-of-programming

Granularity of Parallel Memories

Thermal management of a many-core processor under fine-grained parallelism

The compiler for the XMTC parallel language: Lessons for compiler developers and in-depth description

A PRAM-on-chip vision