Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At nominal operating voltage, the 5-nm node has higher SER than the 7-nm node for all three particle types, with increases of 148%, 168%, and 26%, respectively. The overall SER for the 5-nm node was ~2X greater than that of the 7-nm node, because the reduction in critical charge was higher than that in collected charge. For alpha particle exposures, temperature effects on SER were more prominent for the 5-nm node than both the 7-nm and 16-nm node. Relative contribution of alpha particle SER increases with scaling, and it accounts for 13% of the overall SER at the 5-nm node.

Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment

Integrated circuits are expected to operate across a wide range of temperatures and supply voltages. At the 7-nm FinFET technology node, the self-heating of individual transistors may further increase local temperatures on a die. The combined effects of supply voltage variations and elevated temperatures on soft-error rates for the 7-nm node are investigated. Results show increased sensitivity to soft errors at reduced supply voltage and elevated temperature conditions due to decreased charge collection.

Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology

Very Long Instruction Word, or VLIW, architectures have received much attention in specific-purpose applications such as scientific computation, digital signal processing, and even safety-critical systems. Several compilation techniques for VLIW architectures have been proposed in order to improve the performance, but there is a lack of research to improve reliability against soft errors. Instruction duplication techniques have been proposed by exploiting unused instruction slots (i.e., NOPs) in VLIW architectures. All the instructions cannot be replicated without additional code lines. Additional code lines are required to increase the number of duplicated instructions in VLIW architectures. Our experimental results show that 52% performance overhead as compared to unprotected source code when we duplicate all the instructions. This considerable performance overhead can be inapplicable for resource-constrained embedded systems so that we can limit the number of additional NOP instructions for selective protection. However, the previous static scheme duplicates instructions just in sequential order. In this work, we propose packing-oriented duplication to maximize the number of duplicated instructions within the same peroformance overhead bounds. Our packing-oriented approach can duplicate up to 18% more instructions within the same performance overheads compared to the previous static duplication techniques.

https://www.mdpi.com/2079-9292/10/15/1835/pdf

Selective Code Duplication for Soft Error Protection on VLIW Architectures

Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At nominal operating voltage, the 5-nm node has higher SER than the 7-nm node for all three particle types, with increases of 148%, 168%, and 26%, respectively. The overall SER for the 5-nm node was ~2X greater than that of the 7-nm node, because the reduction in critical charge was higher than that in collected charge. For alpha particle exposures, temperature effects on SER were more prominent for the 5-nm node than both the 7-nm and 16-nm node. Relative contribution of alpha particle SER increases with scaling, and it accounts for 13% of the overall SER at the 5-nm node. 

Scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7-nm process. Neutron SER tests across process corners show that the faster process corner SER is up to $2\times$ higher than the slower process corner SER in 7-nm and 5-nm FinFETs. The process corner dependence of SER is attributed to differences in propagation delay and single-event transient pulse-widths.

Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs

SRAM SER measurements across technology nodes indicate that while scaling from planar processes down to the 7-nm FinFET process provided a reduction in the per-bit SER at every node, subsequent scaling to the 5-nm FinFET process results in an increase in the per-bit SER relative to the 7-nm FinFET process. Extensive data collected across a range of supply voltages show strong exponential bias dependence of SRAM SER for FinFET processes, but the rate of increase in SER as supply voltage is reduced is lower for the 5-nm process compared to the 7-nm. Simulations and modeling indicate that variations in the critical charge ( $Q_{crit}$ ) is the key reason for the observed trends.

V. Chaudhary

Papers

Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET