Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap Cov and fringing Cif+Cof capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

A new relaxation-time-approximation-based nonquasi-static (NQS) MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static description of the MOSFET. The model is implemented in two widely used circuit simulators and is tested for speed and convergence. It is verified by comparison with technology computer-aided design simulations and experimental data and by application of a recently developed benchmark test for NQS MOSFET models.

Accurate RTA-Based Nonquasi-Static MOSFET Model for RF and Mixed-Signal Simulations

Electric double layer transistors (EDLTs) have unique impedance properties. As the transport of charge in the semiconductor and of ions in the electrolyte involve different time scales, the gate-to-channel equivalent capacitance changes dramatically with frequency. An important feature is the coupling between the capacitance and the channel conductance in the frequency range of interest due to the relatively large time constant of the charging process. This paper presents a systematic study of these EDLT properties. An equivalent-circuit model is proposed that provides reasonable physical explanations and shows good agreement with the experimental results.

Coupling of channel conductance and gate-to-channel capacitance in electric double layer transistors

A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. The dopant in the source-drain extension is assumed to segregate to the Si/SiO/sub 2/ interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail,.

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

The electrical performance and the hot-carrier degradation behavior of a new type of fully overlapped device called FOND (Fully Overlapped Nitride-etch defined Device) is analyzed and compared to that of conventional LDD devices. Similar current driveability is found for the FOND devices compared to conventional LDD devices although in the FOND device significantly smaller concentrations are used for the lightly doped n/sup -/-regions. For the overlapped device, a higher gate and overlap capacitance is found, originating from a larger poly length and self-alignment of the junction implant to the poly. For identical voltage conditions, this is reflected in a somewhat lower ring oscillator speed, compared to the LDD case. Concerning reliability, it is shown that deep submicron FOND devices can easily exceed the lifetime of the conventional LDD devices by two orders of magnitude. Based on experimental and simulation results, this higher hot-carrier resistance is explained by a smaller hot-carrier generation and a lower sensitivity of the overlapped device to hot-carrier damage. For the nMOS transistors, the lower generation of damage is the result of the lower lateral electric field due to the low n/sup -/ concentration and the overlap of the polysilicon gate on the n/sup -/ region while the suppressed sensitivity is due to the complete overlap. Compared to LDD devices, the use of fully overlapped devices creates a wider process and reliability margin that can be used to optimize other electrical parameters.

Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

The dependence of the gate capacitance C gds on biasing voltages in currentless regime is discussed for nMOS and pMOS devices The components of the overlap capacitance are extracted as well as the effective poly and channel length The influence of processing conditions on the overlap capacitance is shown

http://ieeexplore.ieee.org/iel5/5435865/5435866/05436120.pdf

Characterisation of the Overlap Capacitance of Submicron LDD MOSFETs

A new model of the gate-to-channel capacitance is proposed including the transmission line effects, not only for strong inversion but also for moderate and weak inversion regimes, which gives a good description of experimental capacitance curves. This is achieved by expressing the channel conductance in function of the inversion layer concentration. Quantum effects in the distribution of the inversion charge are taken into account by the introduction of a mean centroid, which is related to an effective capacitance area. This effective area is smaller than the real one due to nonuniform, surface conductivity, which is attributed to a random doping distribution giving fluctuations of the surface potential.

http://ieeexplore.ieee.org/iel5/5435100/5435101/05436073.pdf

Closed-Form Frequency Dependent Gate-to-Channel Capacitance Model for Submicron MOSFET's

The effective thickness of the inversion layer, expressed in terms of the inversion charge centroid, is determined by capacitance measurements in the weak, moderate and strong inversion regimes using a new model for the gate-to-channel capacitance which takes into account quantum and transmission line effects in all the regimes It is shown that the extracted inversion-layer thickness, using the capacitance-voltage method in a typical frequency range of 10–100 kHz, is unambiguous only for short channel metal-silicon dioxide-semiconductor field effect transistors with channel length Lm less than 1 μm For long channel devices having Lm>(5–10) μm the extraction is very difficult due to the dominant impact of the transmission line effect on the measured capacitance value The effective inversion-layer thickness is found to follow a 1/Ninvm law where Ninv is the inversion-layer concentration (m≅1/3 in the weak inversion regime, m=1/2–1 in moderate inversion regime and m=1/3 in the strong inversion regime) In the strong inversion regime the effective inversion-layer thickness is exactly equal to the real inversion-layer centroid which can be rather accurately described, as is shown, using the electric quantum limit approximation In the moderate and weak inversion regimes the dependence can be explained in terms of the real average charge centroid and an effective conducting area under the gate which is smaller than the real area due to fluctuations of the surface potential The surface potential fluctuation can be attributed to dopant distribution fluctuations

Impact of the transmission line properties of a metal-ultrathin silicon dioxide-semiconductor field-effect transistor on the extracted inversion-layer thickness

V. I. Kol’dyaev

Papers

Characterisation of the Overlap Capacitance of Submicron LDD MOSFETs

Closed-Form Frequency Dependent Gate-to-Channel Capacitance Model for Submicron MOSFET's

Impact of the transmission line properties of a metal-ultrathin silicon dioxide-semiconductor field-effect transistor on the extracted inversion-layer thickness