The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300/spl deg/C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog VLSI in this temperature range. However practical operation of silicon power devices at ambient temperatures above 200/spl deg/C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

High-temperature electronics - a role for wide bandgap semiconductors?

Silicon Carbide (4H-SiC), power UMOSFETs were fabricated and characterized from room temperature to 200/spl deg/C. The devices had a 12-/spl mu/m thick lightly doped n-type drift layer, and a nominal channel length of 4 /spl mu/m. When tested under Fluorinert/sup TM/ at room temperature, blocking voltages ranged from 1.0 kV to 1.2 kV. Effective channel mobility ranged from 1.5 cm/sup 2//V.s at room temperature with a gate bias of 32 V (3.5 MV/cm) up to 7 cm/sup 2//V.s at 100/spl deg/C with an applied gate bias of 26 V (2.9 MV/cm). Specific on-resistance (R/sub on,sp/) was calculated to be as low as 74 m/spl Omega/.cm/sup 2/ at 100/spl deg/C under the same gate bias.

1.1 kV 4H-SiC power UMOSFETs

The transconductance of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is typically much lower in devices fabricated on the 4H-SiC polytype compared to 6H. It is believed that this behavior is caused by extreme trapping of inversion electrons due to a higher density of traps Dit at the SiC/SiO2 interface in 4H-SiC. Here we present an approach for profiling Dit versus energy in the band gap using a modified capacitance–voltage technique on large-area MOSFETs. We find that Dit increases towards the conduction band edge Ec in both polytypes, and that Dit is much higher in 4H- compared to 6H-SiC for devices fabricated in the same process lot.

Interface trap profile near the band edges at the 4H-SiC/SiO2 interface

The electron mobility and free electron density have been measured in 4H– and 6H–SiC metal-oxide-semiconductor inversion layers using the Hall effect. The 4H–SiC inversion layers are found to have very poor conductance which is caused by severe trapping of electrons at the Si/SiO2 interface. The trapping causes reduced conductance through a reduction in the number of free electrons in the inversion layer, and also because of a drop in the mobility due to increased Coulombic scattering.

Hall mobility and free electron density at the SiC/SiO2 interface in 4H–SiC

Extreme temperature semiconductor integrated circuits (ICs) are being developed for use in the hot sections of aircraft engines and other harsh-environment applications well above the 300 °C effective limit of silicon-on-insulator IC technology. This paper reviews progress by the NASA Glenn Research Center and Case Western Reserve University (CWRU) in the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs fabricated and packaged by NASA have now demonstrated thousands of hours of continuous 500 °C operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Design, modeling, and characterization of transistors and circuits at temperatures from 24 °C to 500 °C are also described. CWRU designs for improved extreme temperature SiC JFET differential amplifier circuits are demonstrated. Areas for further technology maturation, needed prior to beneficial system insertion, are discussed. Optical micrograph of a 500 °C durable 6H-SiC JFET differential amplifier IC chip fabricated at NASA prior to packaging. Digitized waveforms measured during the 1st (solid black) and 6519th (dashed grey) hour of 500 °C operational testing show no change in output characteristics.

Extreme temperature 6H-SiC JFET integrated circuit technology

The research and development activities carried out to demonstrate the status of MOS planar technology for the manufacture of high temperature SiC ICs will be described. These activities resulted in the design, fabrication and demonstration of the world's first SiC analog IC—a monolithic MOSFET operational amplifier. Research tasks required for the development of a planar SiC MOSFET IC technology included: characterization of the SiCSiO2 interface using thermally grown oxides; high temperature (350°C) reliability studies of thermally grown oxides; ion implantation studies of donor (N) and acceptor (B) dopants to form junction diodes; epitaxial layer characterization; device isolation methods; and finally integrated circuit design, fabrication and testing of the world's first monolithic SiC operational amplifier IC. High temperature circuit drift instabilities at 350°C were characterized. These studies defined an SiC depletion model MOSFET IC technology and outlined tasks required to improve all types of SiC devices.

Silicon carbide MOSFET technology

The research and development activities carried out to demonstrate the status of MOS planar technology for the manufacture of high temperature SiC ICs will be described These activities resulted in the design, fabrication and demonstration of the World's first SiC analog IC - a monolithic MOSFET operational amplifier Research tasks required for the development of a planar SiC MOSFET IC technology included characterization of the SiC/SiO 2 interface using thermally grown oxides; high temperature (350°C) reliability studies of thermally grown oxides; ion implantation studies of donor (N) and acceptor (B) dopants to form junction diodes: epitaxial layer characterization; N channel inversion and depletion mode MOSFETs ; device isolation methods and finally integrated circuit design, fabrication and testing of the World's first monolithic SiC operational amplifier IC These studies defined a SiC n-channel depletion mode MOSFET IC technology and outlined tasks required to improve all types of SiC devices For instance, high temperature circuit drift instabilities at 350 °C were discovered and characterized This type of instability needs to be understood and resolved because it affects the high temperature reliability of other types of SiC devices Improvements in SiC wafer surface quality and the use of deposited oxides instead of thermally grown SiO2 gate dielectrics will probably be required for enhanced reliability The slow reverse recovery time exhibited by n + -p diodes formed by N ion implantation is a problem that needs to be resolved for all types of planar bipolar devices The reproducibility of acceptor implants needs to be improved before CMOS ICs and many types of power device structures will be manufacturable

V. Krishnamurthy

Papers

Silicon carbide MOSFET technology

Silicon Carbide MOSFET Integrated Circuit Technology