The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300/spl deg/C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog VLSI in this temperature range. However practical operation of silicon power devices at ambient temperatures above 200/spl deg/C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

High-temperature electronics - a role for wide bandgap semiconductors?

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Methods and apparatus for measuring analytes

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Materials, systems and methods for optoelectronic devices

An analog line store comprises a bank of storage capacitors n in number, an n:1 read multiplexer for sequentially sampling from the n storage capacitors as part of a read-then-write operation, a 1:n write multiplexer for sequentially sampling to the n storage capacitors as a further part of the read-then-write operation, and a scanning register for generating control signals for the write multiplexer and the read multiplexer. The storage capacitors have similar capacitances that are substantially invariant with change in stored charge. Such an analog line store is integrated together with a solid-state imager array to provide for the cancellation of fixed pattern noise from the imager video output signal.

Fixed-pattern noise correction circuitry for solid-state imager

The research and development activities carried out to demonstrate the status of MOS planar technology for the manufacture of high temperature SiC ICs will be described. These activities resulted in the design, fabrication and demonstration of the world's first SiC analog IC—a monolithic MOSFET operational amplifier. Research tasks required for the development of a planar SiC MOSFET IC technology included: characterization of the SiCSiO2 interface using thermally grown oxides; high temperature (350°C) reliability studies of thermally grown oxides; ion implantation studies of donor (N) and acceptor (B) dopants to form junction diodes; epitaxial layer characterization; device isolation methods; and finally integrated circuit design, fabrication and testing of the world's first monolithic SiC operational amplifier IC. High temperature circuit drift instabilities at 350°C were characterized. These studies defined an SiC depletion model MOSFET IC technology and outlined tasks required to improve all types of SiC devices.

Silicon carbide MOSFET technology

A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode. An oxide layer extends over the second SiC layer with at least a portion of the oxide layer positioned between the MOSFET electrode contacts. A MOSFET gate electrode is positioned over the oxide layer, and coupling means are provided for electrically couping one of the source, drain, and gate electrodes to one of the resistor electrodes.

Fabrication of silicon carbide integrated circuits

The research and development activities carried out to develop a SiC flame sensor for gas turbines utilized for power generation are discussed. These activities included the fabrication and characterization of SiC UV photodiodes and small SiC signal diodes as well as the designing and testing of production flame detector assemblies. The characteristics that make this solid state flame detector particularly useful for dry low NOx (DLN) premixed oil and natural gas fuels will be described. Since this device provides both analog dc and ac output signals, turbine combustor mode tracking, combustion flame dynamics and flame intensity tracking have been demonstrated. Sensors designed for production have been built, qualified and field tested. These sensors are now being installed in gas turbine power plants and are a component part of the turbine control system. This development has resulted in the first commercialized turbine control application to use SiC electronic devices.

SiC flame sensors for gas turbine control systems

The charge-injection device (CID) imaging technique employs intracell transfer and injection to sense photon-generated charge at each sensing site. Sites are addressed by an X-Y coincident-voltage technique that is not restricted to standard scanning. Free-format (random) site selection is possible. An epitaxial structure provides a buried collector to prevent recollection of the injected charge. In sequential injection, the charge is injected into the substrate and the resulting displacement current sensed. In parallel injection, the functions of signal charge detection and injection have been separated. The injection operation is used to reset (empty) the charge storage capacitors after line readout has been completed. Nondestructive readout (NDRO) is possible by deferring the injection operation. Low-loss NDRO operation has been achieved using a cooled imager. High sensitivity, low dark current, high modulation transfer function (MTF), and low blooming are some additional advantages of sensing signal charge levels within the array. Compared to the charge-coupled device (CCD), the CID approach results in a relatively high output capacitance; however, this is not considered to be a performance-limiting factor for most imaging applications.

Gerald J. Michon

Papers

Fixed-pattern noise correction circuitry for solid-state imager

Silicon carbide MOSFET technology

Fabrication of silicon carbide integrated circuits

SiC flame sensors for gas turbine control systems

Charge-injection imaging: Operating techniques and performances characteristics