OUTPU T 29 OUTPU T 30 OUTPU T 31 OUTPU T 32 OUTPU T 25 OUTPU T 26 OUTPU T 27 OUTPU T 28 OUTPU T 21 OUTPU T 22 OUTPU T 23 OUTPU T 24 OUTPU T 17 OUTPU T 18 OUTPU T 19 OUTPU T 20 OUTPU T 13 OUTPU T 14 OUTPU T 15 OUTPU T 16 OUTPU T 9 OUTPU T 10 OUTPU T 11 OUTPU T 12 OUTPU T 5 OUTPU T 6 OUTPU T 7 OUTPU T 8 OUTPU T 1 OUTPU T 2 OUTPU T 3 OUTPU T 4 29 30 31 32 25 26 27 28 21 22 23 24 17 18 19 20 13 14 15 16 9

A User’s Guide

Small, light weight and multifunctional electronic components are attracting much attention because of the rapid growth of the wireless communication systems and microwave products in the consumer electronic market. The component manufacturers are thus forced to search for new advanced integration, packaging and interconnection technologies. One solution is the low temperature cofired ceramic (LTCC) technology enabling fabrication of three-dimensional ceramic modules with low dielectric loss and embedded silver electrodes. During the past 15 years, a large number of new dielectric LTCCs for high frequency applications have been developed. About 1000 papers were published and ∼500 patents were filed in the area of LTCC and related technologies. However, the data of these several very useful materials are scattered. The main purpose of this review is to bring the data and science of these materials together, which will be of immense help to researchers and technologists all over the world. The comme...

Low loss dielectric materials for LTCC applications: a review

Solder joint fatigue models: review and applicability to chip scale packages

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The dies (124) are attached to the interposer after the attachment of the interposer to the BT substrate. In sequential soldering operations, the solder hierarchy is maintained by dissolving some material (e.g. copper) in the solder during soldering to raise the solder's melting temperature. For example, all of the solders may initially have the same melting temperature, but each solder's melting temperature is increased during soldering to prevent the solder from melting in the subsequent soldering operations.

Packaging substrates for integrated circuits and soldering methods

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.2) are inserted into these vias to provide a strong connection.

Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities

This paper reviews thermal management challenges encountered in a wide range of electronics cooling applications from large-scale (data center and telecommunication) to small-scale systems (personal, portable/wearable, and automotive). This paper identifies drivers for progress and immediate and future challenges based on discussions at the 3rd Workshop on Thermal Management in Telecommunication Systems and Data Centers held in Redwood City, CA, USA, on November 4–5, 2015. Participants in this workshop represented industry and academia, with backgrounds ranging from data center thermal management and energy efficiency to high-performance computing and liquid cooling, thermal management in wearable and mobile devices, and acoustic noise management. By considering a wide range of electronics cooling applications with different lengths and time scales, this paper identifies both common themes and diverging views in the thermal management community.

/pdf/electronics-thermal-management-in-information-and-2cspk9wkyv.pdf

Electronics Thermal Management in Information and Communications Technologies: Challenges and Future Directions

The fatigue life of an underfilled flip-chip package has been evaluated using the Coffin-Manson relation and finite element modeling (FEM)-computed solder shear strain for typical flip-chip structures. In the course of this effort, numerical simulations were performed for underfill materials of varying thermo-structural properties, two chip sizes, and two solder bump heights. The results were used to examine the parametric sensitivity of the thermal strain in the solder joints and the axial, as well as shear stress in the underfill material. The predicted improvement in the number of cycles-to-failure of the underfilled flip-chip was found to agree with empirical observation. However, the maximum improvement achievable by underfilling was found to be limited by the adhesion strength of the underfill material.

Coffin-Manson fatigue model of underfilled flip-chips

The continuing drive toward high-density, low-profile Integrated Circuit packaging has accelerated the spread of flip-chip technology to laminated substrates, creating direct chip attach (DCA) configurations. However, the substantial difference in the coefficients of thermal expansion (CTE) between the chip and the laminated substrates makes DCA configurations vulnerable to thermally-induced strains and the resulting solder joint fatigue. The reliability of flip-chip technology is dramatically improved by "underfilling" the gap between the chip and substrate with epoxy. The present effort is aimed at exploring the benefits of underfilling in DCA configurations. The thermo structural behavior of an underfilled DCA is evaluated using FEM and employing an axisymmetric model of a typical DCA structure. Numerical simulations are performed for different sets of underfill material properties. The results are used to determine the parametric sensitivity of the thermal strain in the solder joints and the axial and shear stresses in the underfill material and to define the desirable range of underfill material properties. These results together with the Coffin-Manson relation are used to predict the theoretical improvement in cycles to failure. The results suggest that to minimize fatigue failure, the CTE of an underfill material should match that of solder material and its Young's Modulus should be as high as the adhesion strength of the underfill allows.

Coffin-Manson based fatigue analysis of underfilled DCAs

A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wall is maintained in its conforming location by an adhesive.

Conformal heat spreader

Delamination and/or rupture of the die-attach layer are among the primary failure mechanisms in plastic IC packages and often lower the threshold for other mechanical, as well as electrical, failure mechanisms Die-attach failure is generally caused by the thermal expansion (contraction) mismatch of dissimilar materials and the consequent development of axial and shear stresses in the adhesive and along the material interfaces To enhance the reliability of plastic packaging it is thus desirable to select the most reliable and cost-effective die-attach material Analysis of an ideal tri-material structure, using a force and momentum balance, makes it possible to derive analytical relations for the axial and shear stresses in a die-attach layer Based on these analytical relations, which are validated against FEM results, the critical material properties can be selected and used for the development of Figures-of-Merit (FOM) for material selection These FOMs are then used to evaluate the effects of moisture on the selection of the die-attach materials

Vadim Gektin

Papers

Electronics Thermal Management in Information and Communications Technologies: Challenges and Future Directions

Coffin-Manson fatigue model of underfilled flip-chips

Coffin-Manson based fatigue analysis of underfilled DCAs

Conformal heat spreader

Mechanistic figures of merit for die-attach materials