A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for nicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.

Phase noise and jitter in CMOS ring oscillators

The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of the fin cross-sectional shape has an impact on the device performance. In this paper, the impact of various fin cross-sectional shape on junctionless accumulation mode bulk FinFETs with thin fins and short channel length has been evaluated. Different important device performance parameters such as ON-current (ION), OFF current (IOFF), ratio of ON/OFF current, Threshold voltage (Vth), Subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (gm/Ids), cut-off frequency (fT), and maximum oscillation frequency (fmax) is evaluated for different fin shapes and analyzed. From the analysis, it is understood that shape of the fin cross-section has substantial impact on performance of the device. Improvement in SCEs was noticed in terms of ~ 25% reduction of DIBL and ~ 10% reduction in SS for the device with reduced fin top width. On the other hand, reduced fin top width degrades the RF performance as maximum frequency of oscillation decrease by ~ 10%. An optimal fin structure for the junctionless bulk FinFET is also obtained to have better SCEs and reasonable Analog/RF applications.

Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cds.2016.0287

Low-power and high-speed 13T SRAM cell using FinFETs

The limitation of CMOS to operate under 25nm is a major concern, which is viewed in this paper. Also, scaling issues like leakage current, lower carrier mobility, higher junction capacitance limits the transistor operation is discussed. At lower voltage values, CMOS productive decreases drastically, which reflects on the performance of the circuit to achieve its criteria’s. In the present-day scenario of electronic industry, the speed of the processor is increasing, the urge for speed cache memory is also increasing. In cache memory design, SRAM cell is mainly used, CMOS SRAM Cells are producing more delay and also limitations like mentioned above. Therefore, an alternative preferred choice for SRAM Cells is FinFET, which increases the speed of the Cell by avoiding limitations caused by the bulk CMOS. By considering the advantages of the FinFET, SRAM Cells are implemented in Cadence virtuoso using FinFET 18nm Spectre. In this paper, standard SRAM Cells like 7T, 8T, 9T, and 1oT are simulated and parameters like power, delay, power delay product (PDP), energy-delay product (EDP) are calculated and respective values are presented by varying the voltage (V). SRAM Cells behavior under different voltages is graphically represented. CMOS SRAM Cell values have been taken from previous works of SRAM. By comparing the parameters, a drastic increase in the speed of the FinFET SRAM Cells can be observed over CMOS SRAM Cells.

Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

This paper represents the design and analysis of ring oscillator using cadence virtuoso tool in 45 nm technology. Ring oscillator consists of odd number of stages with feedback circuit which forms a closed loop in which each stage output depends on the previous stage. In this paper, nine stage ring oscillator have been designed with a capacitor of 1 fF at each stage and simulated for various parameters such as delay, noise, jitter and power consumption. Power consumption, jitter, noise have been reduced in nine stage ring oscillator. Periodic steady state response of ring oscillator is also observed. Power consumption is reduced by 18.9 %.

Design and analysis of CMOS ring oscillator using 45 nm technology

Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Sub-threshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

Analysis and design of low power SRAM cell using independent gate FinFET

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated- technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

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Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

In this paper we have proposed a FinFET based 6T static random access memory (SRAM) cell. FinFET devices can be used to improve the performance, reduce the leakage current and power dissipation. The purpose of this article is to reduce the leakage current and leakage power of FinFET based 6T SRAM cell using various techniques in 45 nm technology. FinFET based 6T SRAM cell has been designed and analysis has been carried out for leakage current and leakage power. For low power memory design the most important problem is to minimize the sub-threshold leakage current and gate leakage current. This work introduces a technique based on threshold voltage, gate oxide thickness and power supply setting together to minimize sub-threshold and gate leakage current of 6T SRAM cell. These simulation results are carried out using Cadence Virtuoso Tool at 45 nm technology.

Vandna Sikarwar

Papers

Design and analysis of CMOS ring oscillator using 45 nm technology

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

Analysis and design of low power SRAM cell using independent gate FinFET

Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

Analysis of leakage current and power reduction techniques in FinFET based SRAM cell