Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

Low-Power Digital Signal Processing Using Approximate Adders

An open Educational Design Kit (EDK) which supports a 90nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PCells. It also includes a Digital Standard Cell Library (DSCL) which supports all contemporary low power design techniques; an I/O Standard Cell Library (IOSCL); a set of memories (SOM) with different word and data depths; and a phase-locked loop (PLL). These components of the EDK augment any type of design for educational and research purposes. Though the EDK does not contain any foundry information, it allows real 90nm technology with high accuracy to be implemented in the designs.

Synopsys' open educational design kit: Capabilities, deployment and future

An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a 900-MHz high-frequency-reference (HFR) PLL, and a novel subsampling lock detector (SSLD). The SSLD keeps monitoring the locking status of the SSPLL by sampling the SSPLL output with the HFR 900-MHz reference and automatically controls the SSPLL for frequency acquisition if it loses lock or locks to a wrong 100-MHz harmonic. This is done without using a power-consuming divider-based frequency-locked loop in conventional SSPLL. Due to the relatively low-frequency operation and moderate noise requirement of HFR, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show 8.8-mW power consumption and 228-fs rms jitter with in-band and out-band phase noises of −96.6 dBc/Hz at a 1-MHz offset and −106.9 dBc/Hz at a 10-MHz offset, respectively.

Low-Power and Low-Noise Millimeter-Wave SSPLL With Subsampling Lock Detector for Automatic Dividerless Frequency Acquisition

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Demand for microelectronics products has seen a recent explosion due to their increased adaption in high‐performance data storage, networking, and Internet of Things applications. Not only such products need to provide high performance, they are often integrated in mixed signal environments that include both analog and digital circuits. This has posed a challenge to faculty who teach microelectronics design in senior undergraduate and graduate electrical engineering courses. It is becoming increasingly difficult to upgrade microelectronics curricula, so students are enabled with the proper skills to utilize design tools presently common in the industry. This study provides a mechanism to integrate five state of the art design tools in one single design project. The tools are Custom Compiler, Hewlett Simulation Program with Integrated Circuit, verilog compiler simulator, IC Validator, and Design Complier. Students, through a design project, conduct the design, layout, and simulations of an static random‐access memory array. The project utilizes both the full‐custom and the semi‐custom flows. One full design is created and integrated where students do the design and layout of transistors in specific circuits and generate synthesized circuits automatically from a high‐level description language. This study can serve as a resource for senior undergraduate students, graduate students, faculty, and practicing engineers. Finally, it can help electrical engineering programs meet Accreditation Board for Engineering and Technology students’ outcome (k) which is an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

Integrating multiple state-of-the-art computer-aided design tools in microelectronics circuit design classes

We have developed a full-custom IC design flow based on Synopsys custom design tools and the recently released Synopsys 90nm generic library. The developed design flow can be used for teaching VLSI and digital IC design courses. We have also developed a full-custom design project that was used as a course project in teaching “Digital VLSI Design” course at San Francisco State University. The design project is to design a 4-bit ripple carry adder in a full custom fashion from schematic to layout in the generic 90nm CMOS technology. The developed design flow and the course project provide a very effective hands-on approach to teaching digital IC design and VLSI design in advanced CMOS technologies. The team project was conducted in a competition based format providing great enthusiasm and motivation among the students, enhancing their learning experience. The competition was to achieve the best design quality defined as the product of following design metrics: propagation delay, power dissipation, and layout area for the 4-bit ripple carry adder. The winning team achieved a delay of 82.2ps, power dissipation of 30.7 μW, and layout area of 112.8 μm2 for the 4-bit adder.

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library

The aggressive scaling of CMOS technology toward nanometer lengths contributed to the surfacing of many effects that were not appreciable at the micrometer regime. Among them, Inverted Temperature Dependence (ITD) is certainly the most unusual. It manifests itself as a speed up of CMOS gates when the temperature increases, resulting in a reversal of the worst-case condition, i.e., CMOS gates show the largest delay at low temperatures. On the other hand, for metal interconnects an high temperature still holds as worst case condition. The two contrasting behaviors may invalidate the results obtained through standard design flow which do not consider temperature as an explicit variable in their optimizations. In this paper we focus on the impact of ITD on clock distribution networks (CDN), whose function is vital to guarantee the synchronization among physically spaced sequential components of digital circuits. Using our simulation framework, we characterized the thermal behavior of a clock tree mapped onto an industrial 65nm CMOS technology and obtained using a standard synthesis tool. Results demonstrate the presence of ITD at low operating voltages and open new potential research scenarios into the EDA field.

Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks

A method of receiver and transmitter input/output resistance calibration, using external reference resistor is presented in this paper. The proposed architecture produces a calibration code corresponding to 50-Ohm PVT compensated termination impedance, which is needed to avoid reflections in transmission lines. The presented calibration mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

Receiver/transmitter input/output termination resistance calibration method

The purpose of this work is to add one more circuit into the traditional PLL to define the lock condition. Fully digital lock detector is presented. Presented circuit provides a simple design, process independence and design automation.

Digital lock detector for PLL

This paper presents method of power optimization implemented on RISC architecture ORCA processor with the help of clock gating and multi-threshold approach aimed at significant reduction of dynamic (switching) power and leakage power. The results are compared with previous research implementing other low power technique on the same processor and with standard design.

Vazgen Melikyan

Papers

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library

Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks

Receiver/transmitter input/output termination resistance calibration method

Digital lock detector for PLL

Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor