Showing papers by "Veena Misra published in 2014"

Device Modeling for Understanding AlGaN/GaN HEMT Gate-Lag

Abstract: Using a simple simulation framework, it is shown that a passivation dielectric that minimizes surface leakage and creates a high density of shallow traps at the surface is vital to minimize the formation of the virtual gate and eliminate AlGaN/GaN HEMT gate-lag. Under large negative gate voltage, this is also expected to create higher fields and current crowding at the gate edge, promoting an increase in total gate leakage. While the AlGaN barrier properties are also found to impact gate-lag, the use of a passivation dielectric that minimizes surface leakage can overpower it's influence and suppress current collapse. Access region shrinking and the use of a longer gate are also found to improve gate-lag.

High Mobility 4H-SiC MOSFETs Using Lanthanum Silicate Interface Engineering and ALD Deposited SiO2

Abstract: In this work, we have developed a novel gate stack to enhance the mobility of Si face (0001) 4H-SiC lateral MOSFETs while maintaining a high threshold voltage. The gate dielectric consists a thin lanthanum silicate layer at SiC/dielectric interface and SiO2 deposited by atomic layer deposition. MOSFETs using this interface engineering technique show a peak field effect mobility of 133.5 cm2/Vs while maintaining a positive threshold voltage of above 3V. The interface state density measured on MOS capacitor with lanthanum silicate interfacial layers is reduced compared to the capacitors without the silicate. It is shown that the presence of the lanthanum at the interface reduces the formation of a lower quality SiOx interfacial layer typically formed at the SiC surface during typical high temperature anneals. This better quality interfacial layer produces a sharp SiC/dielectric interface, which is confirmed by cross section Z-contrast STEM images.

Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation

Abstract: Dual floating gate flash memory has been fabricated and characterized to show dynamic operation, non-volatile operation, and simultaneous dynamic and non-volatile operation. The gate stack consists of a thin dielectric separating two floating gates sandwiched between a tunnel dielectric and interpoly dielectric. The quality of the thin dielectric that separates the floating gates is of utmost importance to retain dynamic operation. In this letter, we investigate a dual floating gate memory transistor and show its potential to combine DRAM and flash functionality in the same device.

A novel methodology using pulsed-IV for interface or border traps characterization on AlGaN/GaN MOSHFETs

Abstract: Characterization of traps at a dielectric/AlGaN interface is critical to evaluate the reliability of the dielectric for the gate stack or passivation of an AlGaN/GaN based MOS Heterojunction Field Effect Transistor (MOSHFET). In this work, we propose a new methodology for interface and border traps characterization using simple DC IV, CV and pulsed-IV measurements. Along with a generic UV lamp, we use this technique to characterize both shallow and deep trap concentrations across the entire AlGaN band gap. The resulting analysis of the ALD HfAlO/AlGaN interface reveals a high density of shallow traps (~7×10 13 cm -2 .eV -1 ) and deep traps (10 11 -10 12 cm -2 .eV -1 ) with a characteristic U-shape.

Design and fabrication of high current AlGaN/GaN HFET for Gen III solid state transformer

Abstract: We have successfully designed and fabricated the high current AlGaN/GaN HFET using 4 masks process. We have achieved the maximum on-current of 7.3A at 1.5V with TO-3 power package. Multi-finger cell-design was implemented to achieve high current extraction from specific active area. In addition, the mesa-free design was adopted to reduce the process steps by employing the self-isolation with surrounded Schottky gate. Length of unit finger is 1000um. Total width of multi-finger is 80 mm. The measured Ronsp and breakdown voltage are 3.4mΩ-cm2 and 450V, respectively. Although the designed breakdown voltage (BV) was 600V, BV reduction has been observed after fabrication due to the process variation. However, overall figure of merit of this device is 2 times superior to that of Super Junction Power MOSFET.

Flash MOS‐HFET operational stability for power converter circuits

Abstract: The enhancement mode metal oxide semiconductor heterojuntion field effect transistor with a flash gate stack (Flash MOS-HFET) device structure is demonstrated as the switching device in a boost converter circuit operating at 1 MHz. The Flash MOS-HFET device maintains a constant threshold voltage for the duration of circuit operation at temperatures up to 125 °C. This is the first report of Flash MOS-HFET operation at high temperature without charge loss over time resulting in negative threshold voltage shift. The Flash MOS-HFET structure therefore is not limited by charge loss and can be inserted into power electronic device circuits as a traditional enhancement mode device. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Effect of post deposition annealing for high mobility 4H-SiC MOSFET utilizing lanthanum silicate and atomic layer deposited SiO 2

Abstract: We have demonstrated high mobility Si-face 4H-SiC MOSFET results using a novel lanthanum silicate (LaSiOx) interface engineering and Atomic Layer Deposited (ALD) SiO2. In this work, the impact of post deposition annealing (PDA) conditions on the mobility of MOSFET with LaSiOx is investigated. The sample received 900 °C PDA in nitrous oxide (N2O) ambient shows the highest mobility and higher PDA temperature reduces the peak mobility. Mobility results measured at elevated temperatures show that the electron mobility of the La-containing devices is limited by the phonon scattering as opposed to the coulombic scattering, indicating improved interface properties.

High voltage AlGaN/GaN HFET employing low taper angle field-plate for stable forward blocking capability

Abstract: A new high voltage AlGaN/GaN heterojuction field effect transistor (HFET) employing low taper angle field-plate (LTA-FP) has been proposed and verified experimentally to achieve stable forward blocking capability with low leakage current. Proposed device with a LTA-FP of 10 degrees, fabricated by adopting a new taper etching process, exhibits stable forward blocking capability with low leakage current (2 orders of magnitude smaller) under repetitive high voltage stress, whereas the conventional device with steep FP of 70 degree shows that unstable behavior under the same stress. These experimental results indicate that the proposed LTA-FP suppresses the electric field concentration at the gate edge successfully and is an effective approach to secure the stable blocking characteristics of GaN based high voltage devices.