This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

A low-power interferer-robust mixer-first receiver front end that uses a novel capacitive stacking technique in a bottom-plate N-path filter/mixer is proposed. Capacitive stacking is achieved by reading out the voltage from the bottom plate of N-path capacitors instead of their top plate, which provides a $2\times $ voltage gain after downconversion. A step-up transformer is used to improve the out-of-band (OOB) linearity performance of small switches in the N-path mixer, thereby reducing the power consumption of switch drivers. This article explains the concept of implicit capacitive stacking and analyzes its transfer characteristics. A prototype chip, fabricated in 22-nm fully depleted silicon on insulator (FDSOI) technology, achieves a voltage gain of 13 dB and OOB IIP3/IIP2 of +25/+66 dBm with 5-dB noise figure while consuming only 600 $\mu \text{W}$ of power at $f_{\mathrm{ LO}}=1$ GHz. Thanks to the transformer, the prototype can operate in the input frequency range of 0.6–1.2 GHz with more than 10-dB voltage gain and 5–9-dB noise figure. Thus, it opens up the possibility of low-power software-defined radios.

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A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer

Wideband self-interference cancellation (SIC) in full-duplex (FD) radios requires the achievement of large delays to accurately emulate the SI channel. However, compact, power-efficient, low-loss/noise/distortion nanosecond-scale delays are extremely challenging to achieve on silicon. Passive transmission lines on silicon are lossy and area-intensive and exhibit reduced bandwidths when miniaturized using inductors and capacitors, whereas active approaches are noisy and power-hungry. In this work, we present a technique that leverages switched-capacitor circuits with multiphase clocking to obtain large on-chip delays over wide bandwidths with the low area and power consumption, thus exceeding the delay–bandwidth product (DBW) limits offered by conventional linear time-invariant (LTI) circuits. This technique is demonstrated in an FD receiver with time-interleaved switched-capacitor-based delay cells in RF and BB domains. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 100 MHz–1 GHz with gain tunability of 15–38 dB, a noise figure of 5.4 dB, and power consumption of 31 mW. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0.2–1.1 ns/10–75 ns while consuming 25.5 and 6.5 mW, respectively. These large tunable delays perform FIR-filtering-based cancellation, enabling 30–35-dB integrated SI cancellation over 20 MHz on top of an off-the-shelf ferrite circulator when terminated by a dipole antenna (isolation of 22 dB), and can handle TX power of up to +9 dBm. Under SIC, the RF and BB cancelers degrade the RX noise figure by 1.1 and 0.8 dB, respectively.

A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit

In this article, a 2.4-GHz Bluetooth low-energy (BLE) receiver employing a new quadrature low-noise amplifier (LNA) is presented for low-power low-voltage Internet of Things (IoT) applications. The proposed quadrature LNA consists of a common-source (CS) amplifier with inductive degeneration, an active-type poly-phase filter (PPF), and an LC tank. The proposed active-type PPF between the CS amplifier and the LC tank provides quadrature generation, and the CS amplifier determines and optimizes the overall LNA performance parameters. Moreover, the proposed active-type PPF shares the dc bias current with the CS amplifier, thereby eliminating the necessity for additional current consumption. The implemented BLE receiver is composed of the quadrature LNA, a $G_{m}$ -stage, a double-balanced current-mode passive mixer, a transimpedance amplifier, and an active- RC complex bandpass filter. The proposed design was fabricated in a 65-nm CMOS process and mainly characterized in the BLE operating frequency bands. The receiver achieves a noise figure of 8.2 dB, a conversion gain of 49.5 dB, an image rejection ratio of more than 33 dB, and an IIP3 of −25.75 dBm. The active die area of the implemented receiver is 1.16 mm2, and it draws a bias current of 2.7 mA from a nominal supply voltage of 0.8 V.

2.4-GHz Bluetooth Low Energy Receiver Employing New Quadrature Low-Noise Amplifier for Low-Power Low-Voltage IoT Applications

The gastro-intestinal (GI) tract is a very important part of the human digestive system but remains largely inaccessible for unobtrusive monitoring. Ingestible electronic devices are a very interesting concept to address this need. This paper discusses the current state of ingestible electronic devices and explores the potential they hold to provide unprecedented insight by measuring several aspects of the complex bio-chemical processes that happen in the GI tract in real-time. This will require novel sensor technology capable of measuring relevant markers with adequate specificity and accuracy. In order to be able to scale this functionality down to a form factor of an easily digestible pill, ultra-low-power wireless interface electronics are needed. This poses certain challenges and innovation opportunities related to sensing, wireless communication and powering to enable the next generation of ingestible electronic devices. [2020-0164]

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Miniaturized Electronic Circuit Design Challenges for Ingestible Devices

This paper presents an energy-/area-efficient digitally controlled oscillator (DCO)-based phase-tracking Receiver for Internet-of-Things (IoT) applications. The RX leverages the constant-envelope nature of frequency shift keying modulation adopted in many IoT protocols, e.g., IEEE802.15.4 and Bluetooth low energy (BLE), to enhance the energy efficiency and to reduce the chip area. The proposed RX, with the DCO acting as a local oscillator (LO) and binary frequency feedback, promotes low-power and low-voltage circuit design, while a data-aided carrier-frequency tracking ensures the received carrier stability without a power-/area-hungry phase-locked loop (PLL). The RX avoids a compromise between a power-hungry I/Q LO generation and the image rejection in traditional RXs. An equivalent mathematical model is further presented, which helps to analyze and optimize the frequency response of the proposed RX. Fabricated in 40-nm CMOS, the RX consumes 1.55 mW from a 0.85-V supply and has a −87-dBm sensitivity at 2 Mb/s, which leads to a 0.77-nJ/b energy efficiency and 178-dB RX sensitivity FoM.

Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications

In this article, we present a passive mixer-first receiver front end providing a low-power integrated solution for high interference robustness in radios targeting Internet-of-Things (IoT) applications. The receiver front end employs a novel N-path filter/mixer, a linear baseband amplifier, and a step-up transformer to realize sub-6-dB NF and >20-dBm OB-IIP3 concurrently. The proposed N-path filter/mixer exploits an implicit capacitive stacking principle to achieve passive voltage gain of 3 during down-conversion and high out-of-band linearity simultaneously while using at least 2x less total capacitance for the same RF bandwidth compared to a conventional switch-capacitor N-path filter. Fabricated in 22-nm complementary metal-oxide-semiconductor (CMOS) fully depleted silicon on insulator (FDSOI), the receiver prototype--including a 2:6 transformer--occupies only 0.2 mm² of active area. Operating in the frequency range of 1.8-2.8 GHz, the front end provides a 45-47-dB conversion gain and a baseband bandwidth of 2 MHz. Due to passive voltage gain in the filter/mixer and transformer, the implemented front end consumes only 1.7-2.5 mW of power to achieve <6-dB NF, ~24/60/1 dBm out-of-band IIP3/IIP2/B1dB, respectively.

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3x Voltage Gain

This paper presents a sub-mW mixer-first RF front-end that exploits a novel capacitive stacking technique in an altered bottom-plate N-path filter/mixer to achieve passive voltage gain and high-linearity at low noise figure. Capacitive stacking is realized implicitly by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x gain at the read-out capacitors. Additional passive voltage gain is achieved using impedance upconversion while improving the out-of-band linearity performance of small switches. With no other active circuitry, only clock generation circuits determine the total power consumption of this RF front-end. A prototype is fabricated in GF22 nm FDSOI technology. Operating at f LO = 1 GHz, the prototype achieves a voltage gain of 13 dB, 5 dB Noise Figure and +25/+66 dBm Out-of-band IIP3/IIP2 at 160 MHz offset while consuming only 600 μW of power from a 0.8 V supply.

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A Sub-mW All-Passive RF Front End with Implicit Capacitive Stacking Achieving 13 dB Gain, 5 dB NF and +25 dBm OOB-IIP3

This article presents a multi-receiver cross-correlation technique for (B)FSK receivers, targeting wireless sensor network applications. Here, multiple receiver outputs are pair-wise cross-correlated and the correlated output samples are averaged to lower the noise floor at the receiver output. Compared to a two-receiver cross-correlation, multi-receiver cross-correlation generates more cross-correlated output samples in a given time. Hence it requires a shorter measurement time for a desired noise floor reduction and facilitates a higher data rate for (B)FSK operation. Compared to a single receiver, it improves the linearity and the harmonic interferer tolerance using passive splitters and different LO frequencies in the receiver paths respectively. These theoretical insights are verified with measurements for the first time using a 2- and 3-receiver cross-correlation in a BFSK receiver. Operating at 1GHz and with a data rate of 200kbps, the demonstrator, using sub-mW mixer-first receiver front-ends for power efficiency, achieves −102dBm sensitivity and >40 dB rejection for both narrow and wideband harmonic interferers without any RF filters.

/pdf/multi-receiver-cross-correlation-technique-for-b-fsk-radios-298eox7yun.pdf

Vijaya Kumar Purushothaman

Papers

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer

Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3x Voltage Gain

A Sub-mW All-Passive RF Front End with Implicit Capacitive Stacking Achieving 13 dB Gain, 5 dB NF and +25 dBm OOB-IIP3

Multi-Receiver Cross-Correlation Technique for (B)FSK Radios