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[서평]「Computer Organization and Design, The Hardware/Software Interface」

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

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Vlsi Physical Design From Graph Partitioning To Timing Closure

The discrete cosine transform (DCT), introduced by Ahmed, Natarajan and Rao, has been used in many applications of digital signal processing, data compression and information hiding. There are four types of the discrete cosine transform. In simulating the discrete cosine transform, we propose a generalized discrete cosine transform with three parameters, and prove its orthogonality for some new cases. A new type of discrete cosine transform is proposed and its orthogonality is proved. Finally, we propose a generalized discrete W transform with three parameters, and prove its orthogonality for some new cases. Keywords: Discrete Fourier transform, discrete sine transform, discrete cosine transform, discrete W transform Nigerian Journal of Technological Research , vol7(1) 2012

On discrete cosine transform

At modern technology nodes, improving routability and reducing total wirelength are no longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve timing violations while limiting the impact to the original placement in an effort to achieve timing closure. To improve the timing landscape in localized regions, some latches or nets may require specialized attention that may not be available in other traditional placement flows (e.g., wirelength-driven). To address this problem, the ICCAD-2015 contest encourages advanced research in incremental timing-driven placement, by providing (i) a flexible timing-oriented placement framework, including a publicly-available and high-quality academic timer, (ii) a set of realistic benchmarks that facilitates academic and commercial collaboration, (iii) an evaluation metric that objectively defines the quality of newly-developed algorithms.

ICCAD-2015 CAD Contest in Incremental Timing-driven Placement and Benchmark Suite

Timing-driven placement (TDP) finds new legal locations for standard cells so as to minimize timing violations while preserving placement quality. Although violations may arise from unmet setup or hold constraints, most TDP approaches ignore the latter. Besides, most techniques focus on reducing the worst negative slack and let the improvements on total negative slack as a secondary goal. However, to successfully achieve timing closure, techniques must also reduce the total negative slack, which is known as slack histogram compression. This paper proposes a new Lagrangian Relaxation formulation for TDP to compress both late and early slack histograms. To solve the problem, we employ a discrete local search technique that uses the Lagrange multipliers as net-weights, which are dynamically updated using an accurate timing analyzer. To preserve placement quality, our technique uses a small fixed-size window that is anchored in the initial location of a cell. For the experimental evaluation of the proposed technique, we relied on the ICCAD 2014 TDP contest infrastructure. The results show that our technique significantly reduces the timing violations from an initial global placement. On average, late and early total negative slacks are improved by 85.03% and 42.72%, respectively, while the worst slacks are reduced by 71.55% and 34.40%. The overhead in wirelength is less than 0.1%.

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR) is an effective technique to handle complex constrained optimization problems and therefore has been successfully applied to solve the gate sizing problem. This article proposes an improved Lagrangian relaxation formulation for discrete gate sizing that relaxes timing, maximum gate input slew, and maximum gate output capacitance constraints. Based on such formulation, we propose a hybrid technique composed of three steps. First, a topological greedy heuristic solves the LR formulation. Such a heuristic is applied assuming a slightly increased target clock period (backoff factor) to better explore the solution space. Second, a delay recovery heuristic reestablishes the original target clock with small power overhead. Third, a power recovery heuristic explores the remaining slacks to further reduce power. Experiments on the ISPD 2012 Contest benchmarks show that our hybrid technique provides less leakage power than the state-of-the-art work for every circuit from the ISPD 2012 Contest infrastructure, achieving up to 24p less leakage. In addition, our technique achieves a much better compromise between leakage reduction and runtime, obtaining, on average, 9p less leakage power while running 8.8 times faster.

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

In advanced technology nodes, standard cell pin access is becoming challenging due to a small number of routing tracks and complex design-for-manufacturing constraints. Pin access interference is further exacerbated by unidirectional routing, which is highly preferred to enable high-density metal patterns and comply with self-aligned multiple patterning solutions. Previous manufacturing-aware routing studies simply depend on the router or sequential planning schemes to resolve pin access interference, which introduces significant overhead on solution qualities. Therefore, we propose concurrent pin access optimization techniques to achieve fast and high-quality routing solutions. The concurrent pin access optimization is modeled as a weighted interval assignment problem, which is solved by an optimal integer linear programming formulation and a scalable Lagrangian relaxation algorithm. A concurrent pin access router is implemented while accommodating advanced manufacturing constraints, which outperforms state-of-the-art manufacturing-aware routers with better routability, fewer vias and faster runtime.

Concurrent Pin Access Optimization for Unidirectional Routing

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discreteness of the problem, along with complex timing models, stringent constraints and ever increasing circuit sizes make the problem very difficult to tackle. Lagrangian Relaxation is an effective technique to handle complex constrained optimization problems and therefore has been used for gate sizing. In this paper, we propose an improved Lagrangian Relaxation formulation for leakage power minimization that accounts for maximum gate input slew and maximum gate output capacitance in addition to the circuit timing constraints. We also present a fast topological greedy heuristic to solve the Lagrangian Relaxation Subproblem and a complementary procedure to fix the few remaining slew and capacitace violations. The experimental results, generated by using the ISPD 2012 Discrete Gate Sizing Contest infrastructure, show that our technique is able to optimize a circuit with up to 959K gates within only 51 minutes. Comparing to the ISPD Contest top three teams, our technique obtained on average 18.9%, 16.7% and 43.8% less leakage power, while being 38, 31 and 39 times faster.

Fast and efficient lagrangian relaxation-based discrete gate sizing

Machine learning models have been used to improve the quality of different physical design steps, such as timing analysis, clock tree synthesis and routing. However, so far very few works have addressed the problem of algorithm selection during physical design, which can drastically reduce the computational effort of some steps. This work proposes a legalization algorithm selection framework using deep convolutional neural networks. To extract features, we used snapshots of circuit placements and used transfer learning to train the models using pre-trained weights of the Squeezenet architecture. By doing so we can greatly reduce the training time and required data even though the pre-trained weights come from a different problem. We performed extensive experimental analysis of machine learning models, providing details on how we chose the parameters of our model, such as convolutional neural network architecture, learning rate and number of epochs. We evaluated the proposed framework by training a model to select between different legalization algorithms according to cell displacement and wirelength variation. The trained models achieved an average F-score of 0.98 when predicting cell displacement and 0.83 when predicting wirelength variation. When integrated into the physical design flow, the cell displacement model achieved the best results on 15 out of 16 designs, while the wirelength variation model achieved that for 10 out of 16 designs, being better than any individual legalization algorithm. Finally, using the proposed machine learning model for algorithm selection resulted in a speedup of up to 10x compared to running all the algorithms separately.

/pdf/algorithm-selection-framework-for-legalization-using-deep-70kpjzppit.pdf

Vinicius Livramento

Papers

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Concurrent Pin Access Optimization for Unidirectional Routing

Fast and efficient lagrangian relaxation-based discrete gate sizing

Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning