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Laércio Lima Pilla

Researcher at Universidade Federal de Santa Catarina

Publications -  59
Citations -  819

Laércio Lima Pilla is an academic researcher from Universidade Federal de Santa Catarina. The author has contributed to research in topics: Load balancing (computing) & Bulk synchronous parallel. The author has an hindex of 15, co-authored 56 publications receiving 691 citations. Previous affiliations of Laércio Lima Pilla include University of Grenoble & Universidade Federal do Rio Grande do Sul.

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Evaluation and Mitigation of Radiation-Induced Soft Errors in Graphics Processing Units

TL;DR: Novel insights on GPU reliability are given by evaluating the neutron sensitivity of modern GPUs memory structures, highlighting pattern dependence and multiple errors occurrences and error-correcting code, algorithm-based fault tolerance, and comparison hardening strategies are presented and evaluated on GPUs through radiation experiments.
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Impact of GPUs Parallelism Management on Safety-Critical and HPC Applications Reliability

TL;DR: The Mean Workload and Executions Between Failures metrics are introduced to evaluate the workload or the number of executions computed correctly by the GPU on a realistic application.
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Characterizing Communication and Page Usage of Parallel Applications for Thread and Data Mapping

TL;DR: A profiling method is introduced to establish the suitability of parallel applications for improved mappings that take the memory hierarchy into account, based on a mathematical description of their memory access behaviors.
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Experimental and analytical study of Xeon Phi reliability

TL;DR: An in-depth analysis of transient faults effects on HPC applications in Intel Xeon Phi processors based on radiation experiments and high-level fault injection is presented and it is shown that portions of applications can be graded by different criticalities.
Proceedings ArticleDOI

A Hierarchical Approach for Load Balancing on Parallel Multi-core Systems

TL;DR: NucoLB is introduced, a topology-aware load balancer that focuses on redistributing work while reducing communication costs among and within compute nodes and takes the asymmetric memory access costs present on NUMA multi-core compute nodes, the interconnection network overheads, and the application communication patterns into account in its balancing decisions.