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Vojtech Mrazek

Researcher at Brno University of Technology

Publications -  64
Citations -  1149

Vojtech Mrazek is an academic researcher from Brno University of Technology. The author has contributed to research in topics: Computer science & Genetic programming. The author has an hindex of 13, co-authored 50 publications receiving 598 citations. Previous affiliations of Vojtech Mrazek include Vienna University of Technology.

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Proceedings ArticleDOI

EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods

TL;DR: The EvoApprox8b library provides Verilog, Matlab and C models of all approximate circuits and the error is given for seven different error metrics.
Proceedings ArticleDOI

Design of power-efficient approximate multipliers for approximate artificial neural networks

TL;DR: The paper showed the capability of the back propagation learning algorithm to adapt with NNs containing the approximate multipliers, and a methodology for the design of well-optimized power-efficient NNs with a uniform structure suitable for hardware implementation.
Journal ArticleDOI

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers

TL;DR: This article replaces the exact multipliers in two representative NNs with approximate designs to evaluate their effect on the classification accuracy and shows that using AMs can also improve the NN accuracy by introducing noise.
Proceedings ArticleDOI

ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining

TL;DR: It is demonstrated that efficient approximations can be introduced into the computational path of DNN accelerators while retraining can completely be avoided, and a simple weight updating scheme is proposed that compensates the inaccuracy introduced by employing approximate multipliers.
Proceedings ArticleDOI

autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components

TL;DR: In this paper, the authors propose a methodology for searching, selecting and combining the most suitable approximate circuits from a set of available libraries to generate an approximate accelerator for a given application, using machine learning techniques to create computational models estimating the overall quality of processing and hardware cost.