In recent days, the complexity of software has increased significantly in embedded products in such a way that the verification of Embedded Software (ESW) now plays an important role to ensure the product's quality. Embedded systems engineers usually face the problems of verifying properties that have to meet the application's deadline, access the memory region, handle concurrency, and control the hardware registers. This work proposes a semiformal verification approach that combines dynamic and static verification to stress and cover exhaustively the state space of the system. We perform a case study on embedded software used in the medical devices domain. We conclude that the proposed approach improves the coverage and reduces substantially the verification time.

/pdf/semiformal-verification-of-embedded-software-in-medical-2ngcvlx0un.pdf

Semiformal Verification of Embedded Software in Medical Devices Considering Stringent Hardware Constraints

The transition from single-core to multi-core processors has made multi-threaded software an important subject over the last years in computer-aided verification. Model checkers have been successfully applied to discover subtle errors, but they suffer from combinatorial state space explosion when verifying multi-threaded software. In our previous work, we have extended the encodings from SMT-based bounded model checking (BMC) to provide more accurate support for program verification and to use different background theories and solvers in order to improve scalability and precision in a completely automatic way. We now focus on extending this work to support an SMT-based BMC formulation of multithreaded software which allows the state space to be reduced by abstracting the number of state variables and interleavings from the proof of unsatisfiability generated by the SMT solvers. The core idea of our approach aims to extract the proof objects produced by the SMT solvers in order to control the number of interleavings and to remove logic that is not relevant to a given property. This work aims to develop a new algorithmic method and corresponding tools based on SMT to verify embedded software in multi-core systems.

/pdf/smt-based-bounded-model-checking-for-multi-threaded-software-49wuj8qwz6.pdf

SMT-based bounded model checking for multi-threaded software in embedded systems

On the integration of model-driven design and dynamic assertion-based verification for embedded software

Dependency on the correct operation of embedded systems is rapidly growing, mainly due to their wide range of applications. Their structures are becoming more complex and currently require multi-core processors with scalable shared memory, signal-processing pipelines, and sophisticated software modules to meet increasing computational power, flexibility demands. Additionally, interaction with real-world entities and modern communication capabilities further enhance the mentioned features and give rise to the embedded and cyber-physical systems (ECPS). As a consequence, the reliability of ECPS becomes a key issue during system development. Generally, state-of-the-art verification methodologies for ECPS generate test vectors and use assertion-based verification and high-level processor models, during simulation; however, new challenges arose, such as need for meeting time and energy constraints, handling concurrent software, evaluating implementation-structure choices, ensuring correct system behavior together with physical plants, and supporting new software architectures and legacy designs. This survey deals with the mentioned issues, reviews related literature, and discusses recent advances in symbolic model checking techniques and their applications to control synthesis. Additionally, challenges, problems, and recent advances to ensure correctness and timeliness, regarding ECPS, are discussed. Reliability issues, when developing ECPS, are then considered, as a prominent verification and synthesis application for achieving correct-by-construction systems.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cps.2018.5006

Survey on automated symbolic verification and its application for synthesising cyber-physical systems

This work suggests a method for systematically constructing an environment model for automotive operating systems compliant with the OSEK/VDX international standard by introducing a constraint specification language, OSEK_CSL, and defining its underlying formal models. OSEK_CSL is designed for specifying constraints of OSEK/VDX using a pre-defined set of constraint types identified from the OSEK/VDX standard. Each constraint specified in OSEK_CSL is interpreted as a context-free language and is converted into push-down automata using NuSMV, which allows automated test sequence generation using LTL model checking. This approach supports selective applications of constraints and thus is able to control the "degree" of test sequences with respect to test purposes. An application of the suggested approach demonstrates its effectiveness in identifying safety problems.

Constraint Specification and Test Generation for OSEK/VDX-Based Operating Systems

The amount of software in embedded systems has increased significantly over the last years and, therefore, the verification of embedded software is of fundamental importance. One of the main problems in embedded software is to verify variables and functions based on temporal properties. Formal property verification using model checker often suffers from the state space explosion problem when a large software design is considered. In this paper, we propose two new approaches to integrate assertions in the verification of embedded software using simulation-based verification. Firstly, we extended a SystemC hardware temporal checker with interfaces in order to monitor the embedded software variables and functions that are stored in a microprocessor memory model. Secondly, we derived a SystemC model from the original C program in order to integrate directly with the SystemC temporal checker. We performed a case study on an embedded software from automotive industry which is responsible for controlling read and write requests to a non-volatile memory.

/pdf/verification-of-temporal-properties-in-automotive-embedded-3psi5odfua.pdf

Verification of temporal properties in automotive embedded software

The verification of embedded software has become an important subject over the last years. This work presents a new semiformal verification approach called SofTPaDS. It combines assertion-based and symbolic simulation approaches for the verification of embedded software with hardware dependencies. SofTPaDS shows to be more efficient than the software model checkers in order to trace deep state spaces and improves the state coverage relative to a simulation-based verification tool. We have successfully applied our approach to an industrial automotive embedded software.

Volker Schonknecht

Papers

Verification of temporal properties in automotive embedded software

Semiformal verification of temporal properties in automotive hardware dependent software