Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration.

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Electromagnetic interference (EMI) of system-on-package (SOP)

Design of on-chip decoupling capacitance and modeling of resonance effects in the power supply network of CMOS integrated circuits is addressed. The modeling is based on mathematical limits proving that damping will be low, resulting in resonance unless careful design is used. Design strategies that reduce resonance are discussed. It is shown that an optimal parasitic resistor in series with the decoupling capacitor gives a maximum damping factor of 0.5 and practical values are within the range 0.3-0.4. Examples of digital circuits show that proper design of on-chip decoupling capacitance may reduce the number of bonding wires by an order of magnitude. The modeling and design suggestions are also applicable to mixed-mode circuits. In particular, sampled analog networks benefit with a potentially higher sampling rate if enhanced damping is introduced during design.

Resonance and damping in CMOS circuits with on-chip decoupling capacitance

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

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Ground bounce in digital VLSI circuits

AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.

4 Gbps high-density AC coupled interconnection

A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver

An on-chip capacitor is formed under the bond pad to block the DC level of input signals. Capacitively coupled signals suffer the "zero wander" effect which causes the local DC level on the second plate of the capacitor to be dependent on the bit activity rate. A quantized feedback technique using a self-triggered decision circuit is used to reestablish local DC voltage levels in the receiver and eliminates the "zero wander" effect. The input signals can be detected over a large common mode range independent of the bit activity rate and over a large frequency range. Silicon area and power dissipation are reduced since encoding and decoding of the bit stream is not required. The circuit has been implemented in silicon using a conventional digital 0.5 /spl mu/m CMOS technology. This receiver can detect a 2/sup 31/-1 pseudorandom pattern at 800 Mb/s with no errors and can operate down to a data rate of 2 kHz.

Capacitive coupling and quantized feedback applied to conventional CMOS technology

Measurements of a 0.5 /spl mu/m CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5/spl times/ and 2/spl times/, respectively. A single external resistor is required to set a reference current.

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

An on-chip capacitor which is formed under a bonding pad is used to block the DC level of an external input signal. Quantized feedback using a self-triggered decision circuit is used to establish local DC voltage levels in the receiver and eliminate the "zero wander" effect. Measurement of a 0.5 /spl mu/m CMOS chip has demonstrated that: a BER (Bit Error Rate) test for a 2/sup 31/-1 sequence showed no errors at 600 Mb/s; the circuit detected a low frequency signal of 1 Kb/s indicating that coding is not required; and the input signal can be DC biased anywhere, limited only by the ESD diodes, between VDD and VSS without affecting the final recovered CMOS waveform.

W. Fischer

Papers

Capacitive coupling and quantized feedback applied to conventional CMOS technology

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Capacitive coupling and quantized feedback applied to conventional CMOS technology