In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Recent Advances and Trends in Advanced Packaging

Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (∼830 mm2) to two reticle size (∼1700 mm2). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5th generation CoWoS-S (CoWoS-S5) based on a Si interposer as large as three full reticle size (∼2500 mm2) by a novel 2-way lithography stitching approach. This will accommodate a multiple of logic chips at a total area of 1200 mm2 (with chiplets) together with eight HBM stacks. Besides the dimensional increase of the Si interposer, new features are incorporated to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include an integrated deep trench capacitor (iCap) for enhanced power integrity, 5 layers of sub-micron Cu interconnect with reduced sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2

Both in Mobile and High-performance Computing (HPC) applications, efficient power supply of the processors was and is still being a big challenge for designers. Indeed, for these applications the power consumption is increasing while the power supply voltage is decreasing in alignment with the latest technological nodes (7nm, 5nm, 3nm…). Thus, lowering and flattening the Power Distribution Network (PDN) impedance is more than ever important to mitigate the voltage fluctuation, the resonance and anti-resonance peaks caused by the PDN's components. Such optimization is done by tuning the features of the different decoupling capacitors used along the power path from the power supply down to the processor. So, by increasing the capacitance, lowering the Equivalent Series Inductance (ESL) and adjusting the Equivalent Series Resistance (ESR) of the different decoupling capacitors, one can manage to have a very low and flat PDN impedance. An overview of the existing 3D Silicon Capacitors (Si-Cap) is presented. Comparison with classical decoupling components will be done and different assembly configurations are discussed (Die side, Embedded, Land side). These components bring unprecedented design flexibility and demonstrated significant improvements by reducing the voltage drop and enabling an efficient power noise reduction.

Multi-Terminal Low-ESL 3D Silicon Capacitors as Enabler for Optimized and Flat PDN Design

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV) interposers will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV interposer. Also, some recommendations will be provided. 

Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV Interposers

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV) interposers will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV interposer. Also, some recommendations will be provided.

A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm2 and low leakage current of <1 fA/μm2. The impact of the DTC on power integrity of the logic-HBM2E system is investigated. In the logic core area, the system power delivery network (PDN) impedance and the 1st voltage droop for the CoWoS with the DTC are 93% and 72% lower than those without the DTC. For the HBM2E PHY area, the PDN impedance and simultaneously switching noise (SSN) of VDDQ for the CoWoS with the DTC are 76% and 62% lower than those without the DTC. Moreover, 11.2% and 16.6% unit interval (UI) eye margin are obtained at the data rate of 2.8 and 3.2 Gbps, respectively. These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.

W. T. Chen

Papers

Design and Analysis of Logic-HBM2E Power Delivery System on CoWoS ® Platform with Deep Trench Capacitor