K
Kai-Yuan Ting
Researcher at TSMC
Publications - 25
Citations - 434
Kai-Yuan Ting is an academic researcher from TSMC. The author has contributed to research in topics: Interposer & Electronic circuit. The author has an hindex of 8, co-authored 25 publications receiving 312 citations.
Papers
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Proceedings ArticleDOI
A 16nm FinFET CMOS technology for mobile SoC and computing applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,Liang Min-Chang,T. Miyashita,C.H. Tsai,B. C. Hsu,H. Y. Chen,T. Yamamoto,S.Y. Chang,Vincent S. Chang,C.H. Chang,J.H. Chen,Hou-Yu Chen,Kai-Yuan Ting,Y.K. Wu,K.H. Pan,R.F. Tsui,C.H. Yao,P. R. Chang,H. M. Lien,Tze-Liang Lee,H. M. Lee,W. Chang,T. Chang,R. Chen,M. Yeh,Chun-Kuang Chen,Yuan-Hung Chiu,Y. H. Chen,H. C. Huang,Y. C. Lu,Chang Chih-Yang,Ming-Huan Tsai,C. C. Liu,Kuei-Shun Chen,C. C. Kuo,H. T. Lin,S. M. Jang,Y. Ku +42 more
TL;DR: This is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node and provides 2X logic density and 2X speed gain over 28nm HK/MG planar technology.
Journal ArticleDOI
Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
Shang-Yun Hou,W. Chris Chen,Clark Hu,Christine Chiu,Kai-Yuan Ting,T. S. Lin,W. H. Wei,W. C. Chiou,Vic J. C. Lin,Victor C. Y. Chang,C. T. Wang,Chung-Cheng Wu,Douglas Yu +12 more
TL;DR: CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.
Proceedings ArticleDOI
An enhanced 16nm CMOS technology featuring 2 nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,S.Z. Chang,Liang Min-Chang,T. Miyashita,C.H. Tsai,C.H. Chang,Vincent S. Chang,Y.K. Wu,J.H. Chen,Hou-Yu Chen,S.Y. Chang,K.H. Pan,R.F. Tsui,C.H. Yao,Kai-Yuan Ting,T. Yamamoto,H.T. Huang,Tze-Liang Lee,C. H. Lee,W. Chang,H. M. Lee,Chun-Kuang Chen,T. Chang,R. Chen,Yuan-Hung Chiu,Ming-Huan Tsai,S. M. Jang,Kuei-Shun Chen,Y. Ku +33 more
TL;DR: In this paper, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented to provide additional 15% speed boost or 30% power reduction.
Proceedings ArticleDOI
Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2
P. K. Huang,Calvin Lu,W. H. Wei,Christine Chiu,Kai-Yuan Ting,Clark Hu,C.H. Tsai,Shang-Yun Hou,Wen-Chih Chiou,C. T. Wang,Douglas Yu +10 more
TL;DR: In this article, the authors report the new 5th generation CoWoS-S (CoWoSS5) based on a Si interposer as large as three full reticle size (∼2500 mm2) by a novel 2-way lithography stitching approach.
Proceedings ArticleDOI
Demonstration of a sub-0.03 um 2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,C.H. Chang,V.S. Chang,K.H. Pan,C.H. Tsai,C.H. Yao,T. Miyashita,Y.K. Wu,Kai-Yuan Ting,C. H. Hsieh,R.F. Tsui,R. Chen,Chang-Ta Yang,Huicheng Chang,C.Y. Lee,Kuei-Shun Chen,Y. Ku,S.M. Jang +21 more
TL;DR: In this paper, the smallest fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node was demonstrated.