Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In one aspect of the present invention, an organosilicate glass film is exposed to an ultraviolet light source wherein the film after exposure has an at least 10% or greater improvement in its mechanical properties (i.e., material hardness and elastic modulus) compared to the as-deposited film.

Mechanical Enhancement of Dense and Porous Organosilicate Materials by UV Exposure

Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided. The example gas channel plate includes a heat exchange surface including a plurality of heat exchange structures separated from one another by intervening gaps. The example gas channel plate also includes a heat exchange fluid director plate support surface for supporting a heat exchange fluid director plate above the plurality of heat exchange structures so that at least a portion of the plurality of heat exchange structures are spaced from the heat exchange fluid director plate.

Process feed management for semiconductor substrate processing

A method of forming an insulation film by alternating multiple times, respectively, a process of adsorbing a precursor onto a substrate and a process of treating the adsorbed surface using reactant gas and a plasma, wherein a plasma is applied in the process of supplying the precursor.

Method of forming insulation film by modified PEALD

The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).

Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.

InFO (Wafer Level Integrated Fan-Out) Technology

A new air-gap interconnect scheme with no additional patterning step successfully resolves the issue of unlanded via, and provides good interconnect reliability and improved packaging margin. We demonstrate that the insertion of airgaps in a very low-k dielectric (k=2.5) reduces the RC value of a 0.07um/0.07um comb structure by ∼14%, which is equivalent to an effective dielectric constant about 2.2.

A self-aligned airgap interconnect scheme

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLP's high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

This paper examines the edge direct tunneling (EDT) of electron from n/sup +/ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E/sub OX/ at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E/sub OX/ to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

https://ir.nctu.edu.tw:443/bitstream/11536/29586/1/000169044500022.pdf

Douglas Yu

Papers

InFO (Wafer Level Integrated Fan-Out) Technology

A self-aligned airgap interconnect scheme

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs