The electron mean free path λ and carrier relaxation time τ of the twenty most conductive elemental metals are determined by numerical integration over the Fermi surface obtained from first-principles, using constant λ or τ approximations and wave-vector dependent Fermi velocities vf (k). The average vf deviates considerably from the free-electron prediction, even for elements with spherical Fermi surfaces including Cu (29% deviation). The calculated product of the bulk resistivity times λ indicates that, in the limit of narrow wires, Rh, Ir, and Ni are 2.1, 1.8, and 1.6 times more conductive than Cu, while various metals including Mo, Co, and Ru approximately match the Cu resistivity, suggesting that these metals are promising candidates to replace Cu for narrow interconnect lines.

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Electron mean free path in elemental metals

Transient liquid phase (TLP) bonding is a relatively new bonding process that joins materials using an interlayer. On heating, the interlayer melts and the interlayer element (or a constituent of an alloy interlayer) diffuses into the substrate materials, causing isothermal solidification. The result of this process is a bond that has a higher melting point than the bonding temperature. This bonding process has found many applications, most notably the joining and repair of Ni-based superalloy components. This article reviews important aspects of TLP bonding, such as kinetics of the process, experimental details (bonding time, interlayer thickness and format, and optimal bonding temperature), and advantages and disadvantages of the process. A wide range of materials that TLP bonding has been applied to is also presented. Partial transient liquid phase (PTLP) bonding is a variant of TLP bonding that is typically used to join ceramics. PTLP bonding requires an interlayer composed of multiple layers; the most common bond setup consists of a thick refractory core sandwiched by thin, lower-melting layers on each side. This article explains how the experimental details and bonding kinetics of PTLP bonding differ from TLP bonding. Also, a range of materials that have been joined by PTLP bonding is presented.

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Overview of transient liquid phase and partial transient liquid phase bonding

As the dimensions of conductors shrink into the nanoscale, their electrical conductivity becomes dependent on their size even at room temperature. Although the behavior varies dramatically as temperatures increase from nanokelvins to hundreds of kelvins, the effect is generally to increase the resistivity above that of bulk material. As such, the underlying size-dependent phenomena have become increasingly important as advanced technologies have shifted their focus first from macro- to microscale and more recently from micro- to nanoscale dimensions. Indeed, the size-dependent increase of electrical resistivity that results from electron scattering on external and internal surfaces of copper conductors has already become technology limiting in modern microelectronics. This article summarizes the phenomena that underlie size effects, focusing on conduction in copper lines in particular. Attention is given to describing key innovations in both theoretical and experimental assessments that have significantly...

Size-Dependent Resistivity in Nanoscale Interconnects

Electrohydrodynamic-inkjet-printed high-resolution complex 3D structures with multiple functional inks are demonstrated. Printed 3D structures can have a variety of fine patterns, such as vertical or helix-shaped pillars and straight or rounded walls, with high aspect ratios (greater than ≈50) and narrow diameters (≈0.7 μm). Furthermore, the formation of freestanding, bridge-like Ag wire structures on plastic substrates suggests substantial potentials as high-precision, flexible 3D interconnects.

High‐Resolution Printing of 3D Structures Using an Electrohydrodynamic Inkjet with Multiple Functional Inks

The need for the development of transparent conductive electrodes (TCEs) supported on flexible polymer substrates has explosively increased in response to flexible polymer-based photovoltaic and display technologies; these TCEs replace conventional indium tin oxide (ITO) that exhibits poor performance on heat-sensitive polymers. An efficient, flexible TCE is required to exhibit high electrical conductance and high optical transmittance, as well as excellent mechanical flexibility and long-term stability, simultaneously. Recent advances in technologies utilizing an ultrathin noble-metal film in a dielectric/metal/dielectric structure, or its derivatives, have attracted attention as promising alternatives that can satisfy the requirements of flexible TCEs. This review will survey the background knowledge and recent updates of synthetic strategies and design rules toward highly efficient, flexible TCEs based on ultrathin metal films, with a special focus on the principal features and available methodologies involved in the fabrication of highly transparent, conductive, ultrathin noble-metal films. This survey will also cover the practical applications of TCEs to flexible organic solar cells and light-emitting diodes.

Ultrathin Metal films for Transparent Electrodes of Flexible Optoelectronic Devices

Influence of the electron mean free path on the resistivity of thin metal films

The electronics industry is increasingly looking to 3D integration in order to address the ever continuing product needs of miniaturization and performance increase for future generation of ICs. Most of these integration schemes require multiple die stacking on top of each other. In this work, transient liquid phase (TLP) bonding technique using Cu-Sn intermetallic is used for die stacking. Fast die to wafer pick and place operation followed by collective bonding process is described here for bonding application. Low temperature stacking is also explored using solid metal bonding (SMB) process and the effect of various cleaning agents on the bonding interface is discussed. Finally, in this paper we report on die stacking using microbumps with dies containing through silicon visa (TSV).

Cu/Sn microbumps interconnect for 3D TSV chip stacking

The size effect in electroplated copper wires has been widely studied recently. However, there is no consensus on the role of various scattering mechanisms. Therefore, an in-depth analysis to reveal the origin of the size effect is needed. In this article, we study the resistivity of fine copper wires whose feature sizes shrink in two dimensions. It is shown that the residual resistivity (at 5 K) increases with decreasing wire width or height and the temperature-dependent resistivity slightly deviates from that of bulk copper. This is mainly attributed to surface scattering rather than grain boundary scattering. In fact, the influence of grain boundary scattering in these well annealed copper wires is relatively small. In addition, for copper wires with a constant height, a linear dependence of the copper resistivity on 1/width (w) or 1/cross-sectional area (A), namely ρ=ρic+c*∕w (or ρ=ρic+c**∕A), is derived from the classic surface and grain boundary scattering models and validated experimentally. In thi...

Analysis of the size effect in electroplated fine copper wires and a realistic assessment to model copper resistivity

3D die stacking is a key technology for enabling 3D integration wherein two or more dies are stacked on top of each other with vertical interconnections. This result in high speed interconnects with reduced noise and crosstalk as compared to wire bonded assemblies. 3D integration may require sequential stacking of multiple dies without disturbing the previously bonded die. This can be achieved by transient liquid phase (TLP) bonding where the melting point of the intermetallic formed after the bonding is much higher than that of the solder itself. In this paper, we demonstrate the feasibility of narrow pitch TLP bonding for the Cu-Sn system in die stacking applications. Furthermore, we explore several process options for cost reduction, throughput enhancement and thermal budget minimization. More than 90% yielding devices are achieved on 40µm pitch peripheral array and 100µm pitch area array dies at 250°C using both flux and No flow UnderFill (NUF) using both die-to-die and die-to-wafer setup. Preliminary bonding results at temperature less than 200°C are also presented.

High density Cu-Sn TLP bonding for 3D integration

In this paper, we present a high yielding 20μm pitch CuSn electroplated microbump flip chip process. The 10μm diameter bumps are organized in an area array, consisting of 440 daisy chains of 1766 bumps each. The 2cm × 2cm flip-chipped dies consist of about 1M bumps in total. The influence of processing materials like seed layer etchants and cleaning agents on the electrical performance of the daisy chains is discussed. Further Ti/Cu versus TiW/Cu seed layers for electroplating are compared. Finally inspection methods for tracing back electrically measured failures are screened.

W. Zhang

Papers

Influence of the electron mean free path on the resistivity of thin metal films

Cu/Sn microbumps interconnect for 3D TSV chip stacking

Analysis of the size effect in electroplated fine copper wires and a realistic assessment to model copper resistivity

High density Cu-Sn TLP bonding for 3D integration

High density 20μm pitch CuSn microbump process for high-end 3D applications