This paper investigates the feasibility of a unified processor architecture to enable error coding flexibility and secure communication in low power Internet of Things (IoT) wireless networks. Error coding flexibility for wireless communication allows IoT applications to exploit the large tradeoff space in data rate, link distance and energy-efficiency. As a solution, we present a light-weight Galois Field (GF) processor to enable energy-efficient block coding and symmetric/asymmetric cryptography kernel processing for a wide range of GF sizes (2m, m = 2, 3, ..., 233) and arbitrary irreducible polynomials. Program directed connections among primitive GF arithmetic units enable dynamically configured parallelism to efficiently perform either four-way SIMD 5- to 8-bit GF operations, including multiplicative inverse, or a wide bit-width (e.g., 32-bit) GF product in a single cycle. To illustrate our ideas, we synthesized our GF processor in a 28nm technology. Compared to a baseline software implementation optimized for a general purpose ARM M0+ processor, our processor exhibits a 5-20 x speedup for a range of error correction codes and symmetric/asymmetric cryptography applications. Additionally, our proposed GF processor consumes 431μW at 0.9V and 100MHz, and achieves 35.5pJ/b energy efficiency while executing AES operations at 12.2Mbps. We achieve this within an area of 0.01mm2.

A Programmable Galois Field Processor for the Internet of Things

Reed–Solomon (RS) codes are a type of forward error correction (FEC) coding that is highly efficient at combating burst errors in received messages. This efficiency has led to its widespread application in error correction in the head tag, often in combination with other channel coders for the construction of robust FEC coding. This brief outlines the design and implementation of a two-mode RS decoder using a simplified step-by-step (SS) algorithm for (255, 239) and (204, 188) RS codes. Calculation of the syndrome determinant in the RS decoder is achieved through Gaussian elimination using a 1-D systolic array with hardware architecture of low complexity, ideally suited for the higher-dimensional matrices used in SS algorithms. The proposed two-mode RS decoder is easily modified with regard to the delay-line buffer size, the delta accumulation and summation module, and the control unit. A two-mode RS decoder with approximately 32 K gates was fabricated using 180-nm complementary metal–oxide–semiconductor technology. Evaluation results confirm that the proposed device consumes only 57 mW at 166 MHz.

Two-Mode Reed–Solomon Decoder Using A Simplified Step-by-Step Algorithm

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Designing Flexible, Energy Efficient and Secure Wireless Solutions for the Internet of Things

The invention provides a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.

A method and apparatus for generating a hardware stream processor design

A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n ≤ 255 with ν errors and ρ erasures correcting capability, 0≤ 2ν+ρ ≤ 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13µm 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.

Design of high-speed errors-and-erasures Reed-Solomon decoders for multi-mode applications

Integrate intellectual properties (IP's) designed for different protocols is always a troublesome task for system integrators. In this paper, we explore efficient methods to generate protocol converters automatically under the consideration of system performance. For the frequency/phase mismatch, we proposed a modified asynchronous FIFO together with our protocol converter. The generated results are verified in Synopsis Verification IP (VIP) environment. The performance and cost of the resulted converter are as efficient as the manual one, ARM Prime Cell.

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Wen-Hsuen Kuo

Papers

Design of high-speed errors-and-erasures Reed-Solomon decoders for multi-mode applications

Efficient protocol converter generation for system integration