Proceedings ArticleDOI
Design of high-speed errors-and-erasures Reed-Solomon decoders for multi-mode applications
Yung-Kuei Lu,Ming-Der Shieh,Wen-Hsuen Kuo +2 more
- pp 199-202
TLDR
A multi-mode Reed-Solomon decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes, making the decoder suitable for VLSI realization.Abstract:
A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n ≤ 255 with ν errors and ρ erasures correcting capability, 0≤ 2ν+ρ ≤ 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13µm 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.read more
Citations
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Proceedings ArticleDOI
A Programmable Galois Field Processor for the Internet of Things
Yajing Chen,Shengshuo Lu,Cheng Fu,David Blaauw,Ronald G. Dreslinski,Trevor Mudge,Hun-Seok Kim +6 more
TL;DR: This paper investigates the feasibility of a unified processor architecture to enable error coding flexibility and secure communication in low power Internet of Things (IoT) wireless networks and presents a light-weight Galois Field (GF) processor to enable energy-efficient block coding and symmetric/asymmetric cryptography kernel processing.
Journal ArticleDOI
Two-Mode Reed–Solomon Decoder Using A Simplified Step-by-Step Algorithm
Chu Yu,Yu-Shan Su +1 more
TL;DR: This brief outlines the design and implementation of a two-mode RS decoder using a simplified step-by-step (SS) algorithm for (255, 239) and (204, 188) RS codes and confirms that the proposed device consumes only 57 mW at 166 MHz.
Dissertation
Designing Flexible, Energy Efficient and Secure Wireless Solutions for the Internet of Things
TL;DR: This document summarizes current capabilities, research and operational priorities, and plans for further studies that were established at the 2015 USGS workshop on quantitative hazard assessments of earthquake-triggered landsliding and liquefaction in the Czech Republic.
References
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Journal ArticleDOI
High-speed architectures for Reed-Solomon decoders
TL;DR: New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented, which require approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm.
Proceedings ArticleDOI
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
Huai-Yi Hsu,An-Yeu Wu +1 more
TL;DR: VLSI design of a reconfigurable multimode Reed Solomon (RS) codec for various high-speed communication systems suitable for multi-mode systems such as the xDSL and the cable modem systems is presented.
Proceedings ArticleDOI
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders
Tong Zhang,Keshab K. Parhi +1 more
TL;DR: A regular hardware architecture is presented to implement the reformulated Berlekamp-Massey algorithm, which can achieve high throughput and an operation scheduling scheme is proposed to further reduce the hardware complexity without loss of throughput.
Journal ArticleDOI
A cellular structure for a versatile Reed-Solomon decoder
Yousef R. Shayan,Tho Le-Ngoc +1 more
TL;DR: A new cellular structure for a versatile Reed-Solomon decoder is introduced based on time domain decoding algorithm and has a very simple structure and hence it is suitable for VLSI designs.
Proceedings ArticleDOI
An area-efficient versatile Reed-Solomon decoder for ADSL
TL;DR: An area-efficient, bit-serial VLSI architecture for the t-error-correcting, (n, k)-scalable Reed-Solomon (RS) decoder in GF(2/sup M/) based on the modified Euclidean algorithm is presented.