Reconfigurability can be thought of as software-defined functionality, where flexibility is controlled predominately through the specification of bit patterns. Reconfigurable systems can be as simple as a single switch, or as abstract and powerful as programmable matter. This paper considers the generalization of reconfigurable systems as an important evolving discipline, bolstered by real-world archetypes such as field programmable gate arrays and software-definable radio (platform and application, respectively). It considers what reconfigurable systems actually are, their motivation, their taxonomy, the fundamental mechanisms and architectural considerations underlying them, designing them and using them in applications. With well-known real-world instances, such as the field programmable gate array, the paper attempts to motivate an understanding of the many possible directions and implications of a new class of system which is fundamentally based on the ability to change.

An Introduction to Reconfigurable Systems

A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.

Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism

This paper presents a novel technique to perform dynamic high-level exploration of a behavioral specification that is being partitioned for a multi-device architecture. The technique, unlike in traditional HLS, performs a global search on the four-dimensional design space formed by multiple partition segments of the behavior. Hence, the proposed technique effectively satisfies the global latency constraint on the entire design, as well as the area constraints on the individual partition segments. Since the technique is based on a rigorous exploration model, it employs an efficient low-complexity heuristic instead of an exhaustive search. We have provided a number of results by integrating the exploration technique with two popular partitioning algorithms: (i) simulated annealing and (ii) Fiduccia-Mattheyses. The proposed technique is highly effective in guiding any partitioning algorithm to a constraint satisfying solution, and in a fairly short execution time. At tight constraint values, the proposed technique has the ability to generate solutions that do not exist in search space of traditional HLS exploration techniques.

A technique for dynamic high-level exploration during behavioral-partitioning for multi-device architectures

The advent of reconfigurable logic arrays facilitates the development of adaptive architectures that have wide applicability as stand- alone intelligent systems. The hardware structure of such architectures can be rapidly altered to suit the changing computational needs of an application during its execution. The power of adaptive architectures has been demonstrated primarily in image processing, digital signal processing, and other areas such as neural networks and genetic algorithms. This chapter discusses the state-of-the-art architectures, their classification, and their applications. In order to effectively exploit adaptive architectures, efficient and retargetable design synthesis techniques are necessary. Further, the synthesis techniques must be fully integrated with design partitioning methods to make use of the multiplicity of reconfigurable devices provided by adaptive architectures. This chapter provides a description of a collection of synthesis and partitioning techniques and their embodiment in the SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) system.

Automated design synthesis and partitioning for adaptive reconfigurable hardware

This paper describes the hardware design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 Xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.

SOM on multi-FPGA ISA board-hardware aspects

The authors examine the interaction of HDL synthesis and multi-FPGA partitioning on designs with varying structural characteristics and HDL coding styles They demonstrate that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs

Wen-Jong Fang

Papers

Integrating HDL synthesis and partitioning for multi-FPGA designs