Showing papers by "Wen-Yan Yin published in 2006"

Modeling of carbon nanotube interconnects and comparative analysis with Cu interconnects

Abstract: Metallic carbon nanotube (CNT) interconnect is regarded as a competitive candidate for next generation of interconnect. An equivalent transmission line model for CNT is proposed in this paper. In our model, the fundamental contact resistance (quantum resistance) is regarded as lumped while the scattering resistance is distributed. The performance of CNT interconnect is examined and compared with the Cu interconnect. It is found that CNT interconnects do not out-perform Cu wire at local interconnect level. However, they have better performance than Cu interconnect at intermediate and global interconnect level. With the technology advancing, their advantages could become greater.

The enhancement of Q factor for patterned ground shield inductors at high temperatures

Abstract: We report on an effective way of using a patterned ground shield (PGS) to enhance the Q factor of on-chip spiral inductors. We fabricated PGS inductors using both 0.18 /spl mu/m and 0.35 /spl mu/m CMOS processes, with M1 and poly strip PGSs, respectively. The strip width and spacing of the PGSs are W/sub g/=0.8 /spl mu/m and S/sub g/=0.45 /spl mu/m, with metal thicknesses of t/sub p/={0.54,0.2} /spl mu/m in the 0.18 /spl mu/m process, and t/sub p/={0.6,0.3} /spl mu/m in the 0.35 /spl mu/m process. The separation distance D between PGS and top metal layer is different in both processes. We found that the Q factor degradation of inductors at high temperatures can be effectively compensated by using PGS. Among all geometric parameters of a PGS in the 0.18 /spl mu/m process, the parameter D is the critical factor for the shielding effectiveness, and M1 PGS is much more efficient than poly strip PGS in improving the inductor performance over the temperature range of 298 K to 358 K. However, in the 0.35 /spl mu/m process the latter is better than the former.

Frequency‐dependent maximum average power‐handling capabilities of single and edge‐coupled microstrip lines on low‐temperature co‐fired ceramic (LTCC) substrates

Abstract: The frequency-dependent maximum average power-handling capabilities (APHCs) of single and edge-coupled microstrip lines (MLs) on low-temperature co-fired ceramic (LTCC) substrates are investigated in this article. Although LTCCs have excellent high-frequency performance, the thermal conductivity is about 2.0–3.0 W/m°C, which is much smaller than that of sapphires, alumina, silicon, and GaAs. The method used to predict the APHC is based on the calculated conductive and dielectric attenuation constants for different modes, and the proposed multilayer thermal model for the temperature rise. Numerical investigations are carried out to examine the effects of geometric and physical parameters on the wideband pulse responses and maximum APHC for single finite-ground thin-film and coupled MLs, respectively. Methodologies to enhance the power-handling capability which are useful in the design of high-density microstrip interconnects on or embedded in multi-layer LTCCs are proposed. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.

Numerical investigation on thermal characteristics of GaN HFETs for high power applications

Abstract: In this paper, numerical investigation on GaN HFETs is carried out using hybrid finite element method (FEM) which combines the FEM with the preconditioned conjugated gradient technique. The maximum temperatures of the HFETs operating under continuous-waves (CW) and pulsed-waves (PW) are both captured accurately. The effects of temperature- dependent thermal conductivities of the materials on the temperature distribution are also studied and compared for different substrate materials, such as sapphire, silicon, and SiC.

Performance degradation of some on-chip finite-ground coplanar waveguide (FGCPW)-built passive devices at high temperature

Abstract: At different temperatures, the performance degradation of on-chip finite-ground coplanar waveguides (FGCPWs) and FGCPW-built meander-line inductors are investigated in this article These passive devices were all fabricated on a double-layer polyimide and GaAs substrates and often used in monolithic microwave integrated circuits It is shown that the increase in temperature causes the increase in series resistance or conductive loss of the metallization planes, and the temperature coefficient of series resistance depends on both frequency and metallization thickness At given metal plane thickness and operating frequency, the conductive attenuation constant increases linearly with increasing temperature Because of the increase in conductive loss, the maximum of Q-factor of each meander-line inductor decreases linearly with increasing temperature While the temperature effect on the parasitic coupling between two parallel FGCPW stubs or between two neighboring inductors can be neglected, even the temperature reaches 438 K © 2006 Wiley Periodicals, Inc Microwave Opt Technol Lett 48: 1754–1759, 2006; Published online in Wiley InterScience (wwwintersciencewileycom) DOI 101002/mop21751

Experimental characterization of hybrid temperature and frequency effects on the performance of transformers on silicon substrate

Abstract: We have performed an experimental characterization of hybrid temperature and frequency effects on the performance of on-chip square transformers. Using measured two-port S-parameters at different temperatures, we extracted and compared the maximum available gain Gmax and fractional power loss Ploss in each of three transformers (with turn numbers of = 2 3, and 4 of the primary and secondary spirals, respectively).We found that, as temperature increases, the transformer performance degrades significantly. This is caused by the increase in the conductive loss of metal tracks and the dielectric loss of silicon substrate. However, beyond a certain temperature, such as at 418 K in the case of = 4, further increase in temperature has little effect on performance, mainly because of the constitutive characteristics of silicon substrate. In addition, the decrease in Gmax and increase in Ploss with temperature depend on the number of turns.

Electromagnetic-Thermal Analysis for Inductances and Eddy Current Losses of On-chip Spiral Inductors on Lossy Silicon Substrate

Abstract: Electromagnetic and thermal analysis for conventional and differential spiral inductors on lossy silicon substrate is rigorously carried out in this paper. Accurate analytical expressions for calculating the frequency- and temperature-dependent inductances and substrate losses due to eddy currents are presented. The simulation results agree well with the measured data. These closed-form expressions offer the great insights into lossy substrate effects as a function of both the frequency and temperature on the performance of on-chip spiral inductors.

Comments on "Modeling of Metallic Carbon-Nanotube Interconnects for Circuit Simulations and a Comparison With Cu Interconnects for Sealed Technologies

Abstract: For original paper, see Raychowdhury and Roy, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.25, no.1, p.58-65, 2006 January

Vertical Tapered Solenoidal Inductor with Zero Spacing

Abstract: Novel vertical tapered solenoidal inductors were designed, fabricated and analyzed in this paper. Due to vertical tapered solenoidal structure, the proposed inductor has small interwire capacitance between adjacent turns and overlap capacitance between the spiral and underpass, which can increase the self resonance frequency of the inductor significantly. The spacing between adjacent turns of this inductor can be minimized to zero, which can save precious physical area on IC boards. For a compact structure, the proposed inductor also has higher inductance as compared with the normal spiral inductor of the same outer and inner dimensions.

Electromagnetic Scattering from an Array of Multiple Slit Coupled Cylindrical Impedance Cavities

Abstract: A generalized procedure was developed to investigate the multiple scattering characteristics of an array of multiple slit-coupled cylindrical impedance cavities for both TM z and TE z incident plane waves. Based on the direct integral equation technique combined with the Galerkin's procedure, the induced current on the impedance walls was expanded in terms of the Chebyshev polynomials of the first kind with fast convergence rate. The far-zone scattered field solutions to such a multiple coupling system were obtainable in analytical form. Numerical calculations were performed to show the variation of the far-zone scattered fields with the geometrical sizes of some typical array design parameters, such as the angular widths of cavity walls or slits, as well as the inductive and capacitive impedance parameters.

Differential VCO design with a wide frequency tuning range

Abstract: New differential stacked spiral inductors were employed in our design of VCOs fabricated using the CMOS 0.18 mum technology in this paper. The frequency tuning range of these VCOs were extended significantly, and the measured oscillation frequencies cover from 1.69 to 2.1375 GHz, with 23.3% tuning range and phase noise about -118.41 dBc/Hz at 1 MHz theoretically. The core current of these VCOs is about 25 mA at 1.8 V supply voltage. What is more, the VCO designed only occupies on-chip area of 365 times 504 mum2, which is much smaller than that of other VCOs reported in the literature recently.