Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Semiconductor devices and methods of manufacture thereof

integrations and challenges of novel high-k gate stacks in advanced cmos technology

A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V t for the PMOS and NMOS FETs.

CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof

Based on 3D simulations, we report a performance assessment of triple- and double-gate FinFETs for high performance (HP), low operating power (LOP) and low standby power (LSTP) logic technologies according to ITRS 65 nm node specifications. The impact of spacer width, lateral source/drain doping gradient, aspect ratio, fin thickness and height along with gate work function on the device performance has been analysed in detail and guidelines are presented to meet the ITRS projections. The design guidelines proposed for a 65 nm node are also examined for a 45 nm node for triple- and double-gate FinFETs. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimized to achieve low values of intrinsic delay. FinFETs should be designed with a higher aspect ratio (~4) along with lower values of fin thickness to achieve ITRS targets for off-current and intrinsic delay. Triple-gate FinFETs show greater design flexibility in selecting important technological and device parameters as compared to double-gate devices. A design window is presented to achieve ITRS targets for the three logic technology requirements with triple- and double-gate FinFETs.

https://iopscience.iop.org/article/10.1088/0268-1242/21/4/002/pdf

Performance assessment of nanoscale double- and triple-gate FinFETs

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

We demonstrate for the first time a continuous and almost linear work function adjustment between 393 and 493eV using Hf/sub x/Mo/sub (1-x)/ binary alloys deposited by co-sputtering In view of the process integration, dual work function metal gate technology using Mo and Hf/sub x/Mo/sub (1-x)/ formed by metal intermixing was proposed Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness

https://ir.nctu.edu.tw:443/bitstream/11536/13608/1/000229356700019.pdf

Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.

https://ir.nctu.edu.tw:443/bitstream/11536/12182/1/000238154200018.pdf

Wu-Lin Ho

Papers

Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination