An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.

Demonstration of L-Shaped Tunnel Field-Effect Transistors

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

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Digital and analog TFET circuits: Design and benchmark

An analytical model on the current–voltage characteristics of cylindrical surrounding gate p-n-i-n tunnel field-effect transistor (TFET) is developed. The model was derived by dividing the source, drain and channel regions into several portions so that some simple approximations for the surface potential across the tunneling junction and the channel can be achieved. Tunneling current is then calculated analytically by integrating the generation rate using the developed surface potential expressions over different regions. The results are verified with TCAD simulations. Good agreements in potential profile, transfer and output characteristics under different biasing conditions and with different device parameters are obtained. The applicability of this model for short-channel device is also discussed.

Analytical model of drain current of cylindrical surrounding gate p-n-i-n TFET

In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

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A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance.

Tunnel field-effect transistor (TFET) has been considered as one of the promising next-generation transistors due to its potentially limit-breaking low subthreshold swing. In this work, we comprehensively examined the effects of the gate-source (G-S) overlap/underlap and the source doping gradient (SDG) of the n -type Si cylindrical gate-all-around (GAA) TFET by the TCAD tools. The simulation results indicate that the G-S overlapping structure has superior device performance than the G-S underlapping structure. However, increasing the G-S overlapping length does not further improve the device performance. Besides, SDG hardly affects the device characteristics of the G-S overlapping TFETs and for the G-S underlapping TFETs, larger SDG can mend the device performance.

Investigation on the Effects of Gate-Source Overlap/Underlap and Source Doping Gradient of n -Type Si Cylindrical Gate-All-Around Tunnel Field-Effect Transistors

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high ION/IOFF ratio (~107) at VDS = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ~108 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec−1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

https://iopscience.iop.org/article/10.1088/0957-4484/25/50/505201/pdf

High performance tunnel field-effect transistor by gate and source engineering.

Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transistors, Tunnel FET (TFET) becomes a most promising one due to its low off current and compatibility with CMOS process. In order to guide the application and the improvement of TFET, in this paper from a circuit-level perspective, utilizing a newly defined benchmarking method, we figured out the frequency-VDD range in which Si TFET circuits show low power advantage over their MOSFET counterparts based on HSPICE simulations using calibrated compact model. A systematic and quantitative analysis was then conducted to further enlarge the application scope of TFET circuits, with a Figure of Merit (FOM) and a guideline for future TFET proposed.

Xia An

Papers

High performance tunnel field-effect transistor by gate and source engineering.

Benchmarking TFET from a circuit level perspective: Applications and guideline