Jiaxin Wang

TL;DR: In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified, and the transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively.

TL;DR: In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average sub-threshold swing (SS), which owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying layer with smaller bandgap materials.

TL;DR: In this paper, a pocket-mSTFET (PMS-TFET) is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications.

TL;DR: The optimal 2D-2D heterostructure for tunneling transistors is presented and elaborately engineered, taking into consideration both electric properties and material stability, and can guide possible development of energy-efficient future-generation electronics.

TL;DR: In this paper, complementary tunnel-FETs (C-TFETs) are integrated with CMOS foundry for high volume production, demonstrating an intrinsic tradeoff between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs.