3-D technology provides many benefits including high density, high bandwidth, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3-D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost is proposed in this paper. Based on probabilistic models, some interesting findings are reported. First, the number of failed TSVs in a tier is usually less than 2 when the number of TSVs in a tier is less than 1000 and less than 5 when the number of TSVs in a tier is less than 10000. Assuming that there are at most 2-5 failed TSVs in a tier. With one redundant TSV allocated to one TSV block, our proposed structure leads to 90% and 95% recovery rates for TSV blocks of size 50 and 25, respectively. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV to 99.4%.

TSV Redundancy: Architecture and Design Issues in 3-D IC

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits : Vertical integration is a novel communications paradigm where interconnect design is a primary focus

An equivalent-circuit model of shield differential through-silicon vias (SDTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. The proposed model is verified using the 3-D full-wave field solver High Frequency Simulator Structure, showing that it is highly accurate up to 100 GHz. Furthermore, a full-wave extraction method for the resistance–inductance–capacitance–conductance (RLCG) parameters of SDTSVs is also proposed in this paper, which can be applied to all of differential transmission lines. It is shown that the results of the RLCG parameters obtained from the full-wave extraction method agree well with that from the analytical calculation up to 100 GHz, further validating the accuracy of the proposed model. Finally, using the proposed model, a deep analysis of electrical characteristics of SDTSVs is carried out to provide helpful design guidelines for them in future 3-D ICs.

Electrical Modeling and Characterization of Shield Differential Through-Silicon Vias

Electromagnetic compatibility-oriented study is performed for accurately characterizing through silicon single-walled carbon nanotube bundle via (TS-SWCNTBV) array in this paper. Based on the modified equivalent lumped-element circuit model of a pair of TS-SWCNTBVs, its forward transmission coefficient, in comparison with copper- and tungsten-based TSVs, is investigated for different metallic fractions of the SWCNTs, with quantum effects treated appropriately. The 3-D transmission-line method (TLM) is further employed for studying mutual couplings in three, four, and nine TS-SWCNTBV arrays, respectively, where the effects of their geometrical and physical parameters on the effective capacitance and conductance are examined in detail. Also, transient coupling noises in different arrays excited by a clock signal, respectively, are predicted and compared, which are useful for the design of high density TS-SWCNTBV arrays with better signal transmission performance.

Electromagnetic Compatibility-Oriented Study on Through Silicon Single-Walled Carbon Nanotube Bundle Via (TS-SWCNTBV) Arrays

Temperature-dependent investigations of circular and square coaxial through-silicon vias (C-TSVs) are carried out in this paper, which can provide an effective solution to suppressing various couplings, such as intra- and intersubstrate, and crosstalk among multi-TSVs. An equivalent lumped-element circuit model is proposed for both C-TSVs, and their parasitic capacitance values, per-unit-height distributed parameters, characteristic impedance values, and S-parameters are characterized and compared numerically for different frequencies and temperatures. Furthermore, self-heating effects in both C-TSVs are investigated with a set of closed-form equations derived for determining their thermal resistances. Their average power handling capabilities are addressed, which are verified using the static finite-element method.

Frequency- and Temperature-Dependent Modeling of Coaxial Through-Silicon Vias for 3-D ICs

Multiphysics characterization of transient electrothermomechanical responses of multilayered stacked through-silicon vias (TSVs) is performed with a modified hybrid time-domain finite-element method. Temperature dependence of most material parameters involved is considered, such as electrical and thermal conductivity, the thermal expansion coefficient, and Young's modulus. Transient temperature and thermal stress accumulation processes are studied in detail for various copper, polycrystalline silicon, and tungsten/polycrystalline silicon TSVs, with different periodic voltage pulses applied. It is shown that there are significant differences in the transient temperature and thermal stress responses among the three types of TSVs, which are all very sensitive to the variation of the surrounding silicon oxide isolation thickness. The algorithm and analysis will be useful in the design of stacked TSVs with high reliability.

Multiphysics Characterization of Transient Electrothermomechanical Responses of Through-Silicon Vias Applied With a Periodic Voltage Pulse

Electrothermal effects in various through silicon via (TSV) arrays are investigated in this paper. An equivalent lumped-element circuit model of a TSV pair is derived. The temperature-dependent TSV capacitance, silicon substrate capacitance and conductance are examined for low-, medium-, and high-resistivity silicon substrates, respectively. The partial-element equivalent-circuit (PEEC) method is employed for calculating per-unit-length (p.u.l.) resistance, inductance, insertion loss and characteristic impedances of copper and polycrystalline silicon (poly-Si) TSV arrays, and their frequencyand temperature-dependent characteristics are treated rigorously. The modified time-domain finite-element method (TD-FEM), in the presence of a set of periodic differential-mode voltage pulses, is also employed for studying transient electrothermal responses of 4and 5-TSV arrays made of different materials, with their maximum temperatures and thermal crosstalk characterized thoroughly.

https://www.jpier.org/pier/pier115/14.11030503.pdf

Electrothermal Effects in High Density through Silicon via (Tsv) Arrays

An equivalent lumped-element circuit model of coaxial TSV is proposed in this paper, in which both frequency- and temperature-dependent elements are extracted using the partial-element equivalent-circuit (PEEC) method One important aspect of coaxial TSV modelling is its capacitance extraction, in which MOS effects are taken into account The circuit model is also reduced to a transmission line one, with its transmission characteristics predicted theoretically for the silicon material but with different resistivities

Electrothermal modeling of coaxial through silicon via (TSV) for three-dimensional ICs

Electrothermal effects in through silicon via (TSV) interconnects are investigated in this paper. The temperature-dependent TSV capacitance is calculated with MOS effect in silicon substrate considered. The per-unit-length resistance and inductance of TSV arrays made of different filling materials are extracted numerically with the partial-element equivalent-circuit (PEEC) method, and insertion losses of some TSV pairs are examined for different silicon substrate resistivities. The electrothermal responses of some TSV arrays made of different materials are also investigated using the modified time-domain finite-element method (TD-FEM).

Xiao-Peng Wang

Papers

Multiphysics Characterization of Transient Electrothermomechanical Responses of Through-Silicon Vias Applied With a Periodic Voltage Pulse

Frequency- and Temperature-Dependent Modeling of Coaxial Through-Silicon Vias for 3-D ICs

Electrothermal Effects in High Density through Silicon via (Tsv) Arrays

Electrothermal modeling of coaxial through silicon via (TSV) for three-dimensional ICs

Electrothermal modelling of through silicon via (TSV) interconnects