Showing papers in "IEEE Transactions on Electron Devices in 2010"

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Abstract: Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits.

All-Printed and Roll-to-Roll-Printable 13.56-MHz-Operated 1-bit RF Tag on Plastic Foils

Abstract: An all-printed rectifier that can provide at least 10 V dc from a 13.56-MHz radio frequency identification (RFID) reader and an all-printed ring oscillator that can generate at least 100 Hz of clock signal to read a 96-bit RFID tag in a second under the dc power provided by the rectifier should first be printable on plastic foils for the realization of roll-to-roll (R2R) printed ultralow cost RFID tags. Here, we describe a practical way to provide all-printed and R2R-printable antenna, rectifiers, and ring oscillators on plastic foils and demonstrate 13.56-MHz-operated 1-bit RF tags. The all-printed and R2R-printable 13.56-MHz 1-bit tags can generate 102.8 Hz of clock signal as the tag approaches the 13.56-MHz RFID reader.

Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

Abstract: Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.

High-Temperature Performance of Silicon Junctionless MOSFETs

Abstract: This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.

Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

Abstract: A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal-oxide-semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low on-current, severe ambipolar behavior, and gradual transition between on- and off -states. To address those issues, the authors have proposed hetero-gate-dielectric TFETs. The proposed device enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.

Recent Advances in ZnO-Based Light-Emitting Diodes

Abstract: ZnO has attracted considerable attention for optical device applications because of several potential advantages over GaN, such as commercial availability of bulk single crystals and a larger exciton binding energy (~60 meV compared with ~25 meV for GaN). Recent improvements in the control of background conductivity of ZnO and demonstrations of p-type doping have intensified interest in this material for applications in light-emitting diodes (LEDs). In this paper, we summarize recent progress in ZnO-based LEDs. Physical and electrical properties, bandgap engineering, and growth of n- and p-type ZnO thin films are also reviewed.

High-Power and High-Efficiency InGaN-Based Light Emitters

Abstract: In this paper, we report on the latest advancements in improving AlGaInN-based visible-light-emitting-diode (LED) efficiency in epitaxy, chip, and package designs. We investigate the fundamental origin of the typical high current ?droop? of efficiency observed in such LEDs. We show that this effect is most likely not caused by incomplete carrier injection or carrier escape but that it is rather a fundamental material property of InGaN/GaN-heterostructure-based light emitters. The droop can be reduced in improved epitaxial LED active-layer designs. We show how this can be achieved by lowering InGaN volume carrier density in multiple quantum wells (MQWs) and thick InGaN layers. Improved epitaxial MQW structures are then combined with a new advanced chip concept. It is optimized for high efficiency at high current operation and arbitrary scalability and can be manufactured at low cost. This is accomplished by improving light-extraction efficiency, homogenizing the emission pattern, reducing forward voltage, and lowering thermal resistance. The improved high current efficiency can be fully exploited by mounting the chip in the highly versatile new OSLON SSL package. It features very stable package materials, a small footprint, and an electrically isolated design decoupling electrical and thermal contacts.

Deep-Ultraviolet Light-Emitting Diodes

Abstract: Compact solid-state deep-ultraviolet (DUV) light-emitting diodes (LEDs) go far beyond replacing conventional DUV sources such as mercury lamps. DUV LEDs enable new applications for air, water, and surface sterilization and decontamination, bioagent detection and identification, UV curing, and biomedical and analytical instrumentation. We review materials growth, device physics, design, fabrication, and performance of DUV LEDs with wavelength ranging from 210 to 365 nm, describe prototype systems for water purification and sterilization, and discuss other emerging applications and systems using DUV LEDs.

Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

Abstract: Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach 106 with a signal swing > 50% of the reading voltage when Ron is beyond 3 M and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design.

Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

Abstract: This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance (RLCG ) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy currents in the silicon substrate. The model is verified against electrostatic measurements as well as a commercial full-wave electromagnetic simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a slight modification (making the effective conductivity complex) is made. Various geometries (as per the International Technology Roadmap for Semiconductors) and prospective materials (Cu, W, and single-walled/multiwalled CNTs) are evaluated, and a comparative performance analysis is presented. It is shown that CNT-bundle-based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to the reduced skin effect in CNT bundle structures. On the other hand, the performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, it is shown that CNTs provide an improved heat dissipation path due to their much higher thermal conductivity. In addition, the improved mechanical robustness and thermal stability of CNTs also favor their selection as TSV materials in emerging 3-D ICs.

Nonpolar and Semipolar III-Nitride Light-Emitting Diodes: Achievements and Challenges

Abstract: It has been several years since InGaN/GaN light-emitting diodes (LEDs) on nonpolar and semipolar orientations were first demonstrated. Prominent performance and inherent potential of these crystallographic orientations have been revealed as bulk-GaN substrates of arbitrary orientations became available for epitaxial device growth. At this point in time, we intend to survey the progress made to date and prospect the future requirements for further device improvements. The discussion begins with a historical background: how nonpolar/semipolar orientations were introduced to III-nitride LEDs and why they are beneficial. The discussion then provides information on elementary crystallography and piezoelectricity in addition to the electronic band structure of wurtzite crystals. Later in this paper, LED reports are collected to develop comprehensive knowledge of the past research efforts and trends. Nonpolar and semipolar orientations provide not only high LED performances, e.g., optical output power and wavelength ranges, but also unique functions, e.g., polarized light emission, which will explore new fields of applications.

A Review on the Physical Mechanisms That Limit the Reliability of GaN-Based LEDs

Abstract: We review the failure modes and mechanisms of gallium nitride (GaN)-based light-emitting diodes (LEDs). A number of reliability tests are presented, and specific degradation mechanisms of state-of-the-art LED structures are analyzed. In particular, we report recent results concerning the following issues: 1) the degradation of the active layer induced by direct current stress due to the increase in nonradiative recombination; 2) the degradation of LEDs submitted to reverse-bias stress tests; 3) the catastrophic failure of advanced LED structures related to electrostatic discharge events; 4) the degradation of the ohmic contacts of GaN-based LEDs; and 5) the degradation of the optical properties of the package/phosphors system of white LEDs. The presented results provide important information on the weaknesses of LED technology and on the design of procedures for reliability evaluation. Results are compared with literature data throughout the text.

Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions

Abstract: This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO2 and high-? dielectrics by comparison to 2-D finite-element simulations.

AlGaN/GaN/GaN:C Back-Barrier HFETs With Breakdown Voltage of Over 1 kV and Low $R_{\scriptscriptstyle{\rm ON}} \times A$

Abstract: A systematic study of GaN-based heterostructure field-effect transistors with an insulating carbon-doped GaN back barrier for high-voltage operation is presented. The impact of variations of carbon doping concentration, GaN channel thickness, and substrates is evaluated. Tradeoff considerations in on-state resistance versus current collapse are addressed. Suppression of the off-state subthreshold drain-leakage currents enables a breakdown voltage enhancement of over 1000 V with a low on-state resistance. Devices with a 5-μm gate-drain separation on semi-insulating SiC and a 7-μm gate-drain separation on n-SiC exhibit 938 V and 0.39 mΩ·cm2 and 942 V and 0.39 m Ω·cmcm2, respectively. A power device figure of merit of ~ 2.3 × 109 V2/Ω·cm2 was calculated for these devices.

Ohmic-Contact Technology for GaN-Based Light-Emitting Diodes: Role of P-Type Contact

Abstract: GaN-based semiconductors are of great technological importance for the fabrication of optoelectronic devices, such as light-emitting diodes (LEDs) and laser diodes. The further improvement of LED performance can be achieved through the enhancement of external quantum efficiency. In this regard, high-quality p-type ohmic electrodes having low contact resistance and high transmittance (or reflectivity), along with thermal stability, must be developed because p-type ohmic contacts play a key role in the performance of LEDs. In this paper, we review recent advances in p-type ohmic-contact technology for GaN-based LEDs. A variety of methods for forming transparent and reflective ohmic contacts are introduced.

On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors

Abstract: Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron-phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.

Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs

Abstract: The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation

Abstract: This paper highlights and experimentally verifies a new source of random threshold-voltage (V_th) fluctuation in emerging metal-gate transistors and proposes a statistical framework to investigate its device and circuit-level implications. The new source of variability, christened work-function (WF) variation (WFV), is caused by the dependence of metal WF on the orientation of its grains. The experimentally measured data reported in this paper confirm the existence of such variations in both planar and nonplanar high-k metal-gate transistors. As a result of WFV, the WFs of metal gates are statistical distributions instead of deterministic values. In this paper, the key parameters of such WF distributions are analytically modeled by identifying the physical dimensions of the devices and properties of materials used in the fabrication. It is shown that WFV can be modeled by a multinomial distribution where the key parameters of its probability distribution function can be calculated in terms of the aforementioned parameters. The analysis reveals that WFV will contribute a key source of V_th variability in emerging generations of metal-gate devices. Using the proposed framework, one can investigate the implications of WFV for process, device, and circuit design, which are discussed in Part II.

Double-Corrugated Rectangular Waveguide Slow-Wave Structure for Terahertz Vacuum Devices

Abstract: A novel rectangular-corrugated waveguide is proposed for submillimeter and terahertz vacuum devices. Two parallel corrugations that are enclosed in a rectangular waveguide create a beam channel that supports an interaction with a cylindrical electron beam. A notable advantage of the double-corrugated rectangular waveguide slow-wave structure (SWS) is the extension of well-established cylindrical beam technology to corrugated waveguide SWSs. The structure is also fully realizable with the most recent microfabrication techniques and is easily assembled. A detailed study to describe the electromagnetic behavior of the presented SWS is performed by 3-D electromagnetic simulation. A 650-GHz backward-wave oscillator and a 227-GHz traveling-wave tube are designed and simulated, by 3-D particle-in-cell code, to highlight the great potential of the double-corrugated rectangular waveguide for submillimeter frequency vacuum devices.

Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics

Abstract: Carbon-based nanomaterials such as metallic single-walled carbon nanotubes, multiwalled carbon nanotubes (MWCNTs), and graphene have been considered as some of the most promising candidates for future interconnect technology because of their high current-carrying capacity and conductivity in the nanoscale, and immunity to electromigration, which has been a great challenge for scaling down the traditional copper interconnects. Therefore, studies on the performance and optimization of carbon-based interconnects working in a realistic operational environment are needed in order to advance the technology beyond the exploratory discovery phase. In this paper, we present the first demonstration of graphene interconnects monolithically integrated with industry-standard complementary metal-oxide-semiconductor technology, as well as the first experimental results that compare the performance of high-speed on-chip graphene and MWCNT interconnects. The graphene interconnects operate up to 1.3-GHz frequency, which is a speed that is commensurate with the fastest high-speed processor chips today. A low-swing signaling technique has been applied to improve the speed of carbon interconnects up to 30%.

Corrugated Rectangular Waveguide Tunable Backward Wave Oscillator for Terahertz Applications

Abstract: A tunable backward wave oscillator (BWO) for terahertz applications is proposed. The use of a corrugated rectangular waveguide as the slow-wave structure permits relevant performance together with full compatibility with microfabrication technologies. The design, done using an analytical electromagnetic model, is fully verified by 3-D particle-in-cell simulations. A 20% tuning bandwidth is obtained at a central frequency of 1 THz, demonstrating more than 100-mW output power.

Erratum: Analytic Model for the Surface Potential and Drain Current in Negative Capacitance Field-Effect Transistors

Abstract: In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance (NC) region could act as a step-up converter of the surface potential in a metal-oxide-semiconductor structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S <; 60mV/dec). In this paper, a comprehensive physics-based surface potential and a drain current model for the NC field-effect transistor are reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. This paper also sheds light on how operation in the NC region can be experimentally detected.

AlGaN/GaN/AlGaN DH-HEMTs Breakdown Voltage Enhancement Using Multiple Grating Field Plates (MGFPs)

Abstract: GaN-based high-electron mobility transistors with planar multiple grating field plates (MGFPs) for high-voltage operation are described. A synergy effect with additional electron channel confinement by using a heterojunction AlGaN back barrier (BB) is demonstrated. Suppression of the OFF-state subthreshold gate and drain leakage currents enables breakdown voltage enhancement over 700 V and a low ON-state resistance of 0.68 mΩ × cm2. Such devices have a minor tradeoff in ON-state resistance, lag factor, maximum oscillation frequency, and cutoff frequency. A systematic study of the MGFP design and the effect of Al composition in the BB is described. Physics-based device simulation results give insight into electric field distribution and charge carrier concentration, depending on the field plate design.

Structural Analysis on Organic Thin-Film Transistor With Device Simulation

Abstract: A 2-D device simulation for organic thin-film transistors (OTFTs) was carried out to reveal the characteristic difference between staggered and planar structures. Assuming the OTFT with Schottky barrier contact, the staggered-structure TFT has more current flow, bigger field-effect mobility, and lower contact resistance than the planar structure. The simulation results indicate that the source electrode of the staggered structure has better ability to supply the current than that of the planar structure.

Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

Abstract: This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (?V th) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ?V th and is therefore proportional to the trend of ?V th. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

Analytical Modeling of a Nanogap-Embedded FET for Application as a Biosensor

Abstract: An analytical model of a nanogap-embedded field-effect transistor, which is termed here simply as a biotransistor, is developed in this study. A surface potential model is attained by solving a 2-D Poisson equation with approximation of a parabolic potential profile along the channel depth. The analytical threshold voltage is then derived from the surface potential model to comprise the unique feature of the biotransistor, which acts as a biosensor. A shift of the threshold voltage was used as a metric to ascertain the sensitivity after the biomolecule interacts with the biotransistor. Various device parameters were investigated in the developed analytical model. The characteristic trend is supported and verified via a simulation. Hence, the proposed model can provide a useful guideline for the optimal design and fabrication of a biotransistor.

High-Voltage n-Channel IGBTs on Free-Standing 4H-SiC Epilayers

Abstract: In this paper, we describe a process for fabricating high-voltage n-channel double-diffused metal-oxide-semiconductor insulated gate bipolar transistors (IGBTs) on free-standing 4H silicon carbide (SiC) epilayers. In this process, all critical layers are epitaxially grown in a continuous sequence. The substrate is then removed, and device fabrication takes place on the carbon face of a free-standing epilayer having a total thickness of about 180 ?m. For a drift layer with doping and thickness values capable of blocking 20 kV, the n-channel IGBT carries 27.3-A/cm2 current at a power dissipation of 300 W/cm2, with a differential on-resistance of 177 m?·cm2. To our knowledge, this is the first detailed report of device fabrication on free-standing SiC epilayers.

Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Abstract: The silicon on thin buried oxide (SOTB) has the smallest V th variation among planar CMOS due to a low-dose channel. This study focuses on evaluating local variability components and searching for the dominant factor after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity is important to reduce both the global and local variations. The local V th variation A Vt was very small, ~ 1.0 and 0.7 mV·?m for NMOS and PMOS, respectively; however, additional unknown factors other than RDF still exist. Silicon-on-insulator thickness variation does not play a major role in ?V th , and the SOTB is scalable to less than 25 nm while maintaining small variability and, hence, low power consumption. The larger variability in NMOS compared to that in PMOS cannot be explained by conventional RDF but seems to be strongly related to channel doping.

Comparison of InGaN-Based LEDs Grown on Conventional Sapphire and Cone-Shape-Patterned Sapphire Substrate

Abstract: To improve the external quantum efficiency, a high-quality InGaN/GaN film was grown on a cone-shape-patterned sapphire substrate (CSPSS) by using metal-organic chemical vapor deposition. The surface pattern of the CSPSS seems to be more helpful for the accommodative relaxation of compressive strain related to the lattice mismatch between GaN and a sapphire substrate because the growth mode of GaN on the CSPSS was similar to that of the epitaxial lateral overgrowth. The output power of a light-emitting diode (LED) grown on the CSPSS was estimated to be 16.5 mW at a forward current of 20 mA, which is improved by 35% compared to that of a LED grown on a conventional sapphire substrate. The significant enhancement in output power is attributed to both the increase of the extraction efficiency, resulted from the increase in photon escaping probability due to enhanced light scattering at the CSPSS, and the improvement of the crystal quality due to the reduction of dislocation.

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Abstract: Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.